Commit 0586ade9 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'loongarch-kvm-6.13' of... 

Merge tag 'loongarch-kvm-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD

LoongArch KVM changes for v6.13

1. Add iocsr and mmio bus simulation in kernel.
2. Add in-kernel interrupt controller emulation.
3. Add virt extension support for eiointc irqchip.
parents 7b541d55 9899b820

.mailmap

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@@ -665,6 +665,7 @@ Tomeu Vizoso <tomeu@tomeuvizoso.net> <tomeu.vizoso@collabora.com> 
Thomas Graf <tgraf@suug.ch>

Thomas Körper <socketcan@esd.eu> <thomas.koerper@esd.eu>

Thomas Pedersen <twp@codeaurora.org>

Thorsten Blum <thorsten.blum@linux.dev> <thorsten.blum@toblux.com>

Tiezhu Yang <yangtiezhu@loongson.cn> <kernelpatch@126.com>

Tingwei Zhang <quic_tingwei@quicinc.com> <tingwei@codeaurora.org>

Tirupathi Reddy <quic_tirupath@quicinc.com> <tirupath@codeaurora.org>

CREDITS

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@@ -1204,6 +1204,10 @@ S: Dreisbachstrasse 24 
S: D-57250 Netphen

S: Germany



N: Florian Fainelli

E: f.fainelli@gmail.com

D: DSA



N: Rik Faith

E: faith@acm.org

D: Future Domain TMC-16x0 SCSI driver (author)

Documentation/admin-guide/kernel-parameters.txt

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@@ -6688,7 +6688,7 @@ 
			0: no polling (default)



	thp_anon=	[KNL]

			Format: <size>,<size>[KMG]:<state>;<size>-<size>[KMG]:<state>

			Format: <size>[KMG],<size>[KMG]:<state>;<size>[KMG]-<size>[KMG]:<state>

			state is one of "always", "madvise", "never" or "inherit".

			Control the default behavior of the system with respect

			to anonymous transparent hugepages.

Documentation/admin-guide/mm/transhuge.rst

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@@ -303,7 +303,7 @@ control by passing the parameter ``transparent_hugepage=always`` or 
kernel command line.



Alternatively, each supported anonymous THP size can be controlled by

passing ``thp_anon=<size>,<size>[KMG]:<state>;<size>-<size>[KMG]:<state>``,

passing ``thp_anon=<size>[KMG],<size>[KMG]:<state>;<size>[KMG]-<size>[KMG]:<state>``,

where ``<size>`` is the THP size (must be a power of 2 of PAGE_SIZE and

supported anonymous THP)  and ``<state>`` is one of ``always``, ``madvise``,

``never`` or ``inherit``.

Documentation/arch/loongarch/irq-chip-model.rst

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@@ -85,6 +85,70 @@ to CPUINTC directly:: 
    | Devices |

    +---------+



Virtual Extended IRQ model

==========================



In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt

go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other

devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual

Extended I/O Interrupt Controller), and then go to CPUINTC directly::



       +-----+    +-------------------+     +-------+

       | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |

       +-----+    +-------------------+     +-------+

                            ^

                            |

                      +-----------+

                      | V-EIOINTC |

                      +-----------+

                       ^         ^

                       |         |

                +---------+ +---------+

                | PCH-PIC | | PCH-MSI |

                +---------+ +---------+

                  ^      ^          ^

                  |      |          |

           +--------+ +---------+ +---------+

           | UARTs  | | Devices | | Devices |

           +--------+ +---------+ +---------+





Description

-----------

V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of

EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can

be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC

interrupts can be routed to up to 256 virtual cpus.



With standard EIOINTC, interrupt routing setting includes two parts: eight

bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection.

For CPU selection there is four bits for EIOINTC node selection, four bits

for EIOINTC CPU selection. Bitmap method is used for CPU selection and

CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in

one EIOINTC node.



With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),

there are two newly added registers with V-EIOINTC.



EXTIOI_VIRT_FEATURES

--------------------

This register is read-only register, which indicates supported features with

V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.



Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it

indicates that CPU Interrupt Pin selection can be normal method rather than

bitmap method, so interrupt can be routed to IP0 - IP15.



Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it

indicates that CPU selection can be normal method rather than bitmap method,

so interrupt can be routed to CPU0 - CPU255.



EXTIOI_VIRT_CONFIG

------------------

This register is read-write register, for compatibility intterupt routed uses

the default method which is the same with standard EIOINTC. If the bit is set

with 1, it indicated HW to use normal method rather than bitmap method.



Advanced Extended IRQ model

===========================