Commit 0708ed7c authored by Allen-KH Cheng's avatar Allen-KH Cheng Committed by Matthias Brugger
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arm64: dts: mt8192: Add dsi node 



Add dsi node for mt8192 SoC.

Signed-off-by: default avatarAllen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220712114046.15574-6-allen-kh.cheng@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent b4b75bac

arch/arm64/boot/dts/mediatek/mt8192.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -1344,6 +1344,25 @@ dither0: dither@1400e000 { 
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;

		};



		dsi0: dsi@14010000 {

			compatible = "mediatek,mt8183-dsi";

			reg = <0 0x14010000 0 0x1000>;

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;

			clocks = <&mmsys CLK_MM_DSI0>,

				 <&mmsys CLK_MM_DSI_DSI0>,

				 <&mipi_tx0>;

			clock-names = "engine", "digital", "hs";

			phys = <&mipi_tx0>;

			phy-names = "dphy";

			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;

			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;

			status = "disabled";



			port {

				dsi_out: endpoint { };

			};

		};



		ovl_2l2: ovl@14014000 {

			compatible = "mediatek,mt8192-disp-ovl-2l";

			reg = <0 0x14014000 0 0x1000>;