Commit 071e5ace authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM driver updates from Olof Johansson:

 - Reset controllers: Adding support for Microchip Sparx5 Switch.

 - Memory controllers: ARM Primecell PL35x SMC memory controller driver
   cleanups and improvements.

 - i.MX SoC drivers: Power domain support for i.MX8MM and i.MX8MN.

 - Rockchip: RK3568 power domains support + DT binding updates,
   cleanups.

 - Qualcomm SoC drivers: Amend socinfo with more SoC/PMIC details,
   including support for MSM8226, MDM9607, SM6125 and SC8180X.

 - ARM FFA driver: "Firmware Framework for ARMv8-A", defining management
   interfaces and communication (including bus model) between partitions
   both in Normal and Secure Worlds.

 - Tegra Memory controller changes, including major rework to deal with
   identity mappings at boot and integration with ARM SMMU pieces.

* tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (120 commits)
  firmware: turris-mox-rwtm: add marvell,armada-3700-rwtm-firmware compatible string
  firmware: turris-mox-rwtm: show message about HWRNG registration
  firmware: turris-mox-rwtm: fail probing when firmware does not support hwrng
  firmware: turris-mox-rwtm: report failures better
  firmware: turris-mox-rwtm: fix reply status decoding function
  soc: imx: gpcv2: add support for i.MX8MN power domains
  dt-bindings: add defines for i.MX8MN power domains
  firmware: tegra: bpmp: Fix Tegra234-only builds
  iommu/arm-smmu: Use Tegra implementation on Tegra186
  iommu/arm-smmu: tegra: Implement SID override programming
  iommu/arm-smmu: tegra: Detect number of instances at runtime
  dt-bindings: arm-smmu: Add Tegra186 compatible string
  firmware: qcom_scm: Add MDM9607 compatible
  soc: qcom: rpmpd: Add MDM9607 RPM Power Domains
  soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's
  soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's
  dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml
  memory: emif: remove unused frequency and voltage notifiers
  memory: fsl_ifc: fix leak of private memory on probe failure
  memory: fsl_ifc: fix leak of IO mapping on probe failure
  ...
parents e083bbd6 2afd1c20

Documentation/devicetree/bindings/arm/rockchip/pmu.txt

deleted100644 → 0
+0 −16
Original line number Diff line number Diff line 
Rockchip power-management-unit:

-------------------------------



The pmu is used to turn off and on different power domains of the SoCs

This includes the power to the CPU cores.



Required node properties:

- compatible value : = "rockchip,rk3066-pmu";

- reg : physical base address and the size of the registers window



Example:



	pmu@20004000 {

		compatible = "rockchip,rk3066-pmu";

		reg = <0x20004000 0x100>;

	};

Documentation/devicetree/bindings/arm/rockchip/pmu.yaml

0 → 100644
+55 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip Power Management Unit (PMU)



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The PMU is used to turn on and off different power domains of the SoCs.

  This includes the power to the CPU cores.



select:

  properties:

    compatible:

      contains:

        enum:

          - rockchip,px30-pmu

          - rockchip,rk3066-pmu

          - rockchip,rk3288-pmu

          - rockchip,rk3399-pmu



  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - rockchip,px30-pmu

          - rockchip,rk3066-pmu

          - rockchip,rk3288-pmu

          - rockchip,rk3399-pmu

      - const: syscon

      - const: simple-mfd



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: true



examples:

  - |

    pmu@20004000 {

      compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";

      reg = <0x20004000 0x100>;

    };

Documentation/devicetree/bindings/firmware/qcom,scm.txt

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ Required properties: 
 * "qcom,scm-ipq4019"

 * "qcom,scm-ipq806x"

 * "qcom,scm-ipq8074"

 * "qcom,scm-mdm9607"

 * "qcom,scm-msm8660"

 * "qcom,scm-msm8916"

 * "qcom,scm-msm8960"

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

+9 −2
Original line number Diff line number Diff line
@@ -54,8 +54,14 @@ properties: 
          - const: arm,mmu-500

      - description: NVIDIA SoCs that program two ARM MMU-500s identically

        items:

      - description: NVIDIA SoCs that require memory controller interaction

          and may program multiple ARM MMU-500s identically with the memory

          controller interleaving translations between multiple instances

          for improved performance.

        items:

          - enum:

              - nvidia,tegra194-smmu

              - const: nvidia,tegra194-smmu

              - const: nvidia,tegra186-smmu

          - const: nvidia,smmu-500

      - items:

          - const: arm,mmu-500
@@ -165,10 +171,11 @@ allOf: 
          contains:

            enum:

              - nvidia,tegra194-smmu

              - nvidia,tegra186-smmu

    then:

      properties:

        reg:

          minItems: 2

          minItems: 1

          maxItems: 2

    else:

      properties:

Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml

+3 −8
Original line number Diff line number Diff line
@@ -30,9 +30,6 @@ properties: 
  "#clock-cells":

    const: 0



  "#phy-cells":

    const: 0



  clocks:

    maxItems: 1
@@ -120,7 +117,6 @@ required: 
  - reg

  - clock-output-names

  - "#clock-cells"

  - "#phy-cells"

  - host-port

  - otg-port
@@ -131,26 +127,25 @@ examples: 
    #include <dt-bindings/clock/rk3399-cru.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    u2phy0: usb2-phy@e450 {

    u2phy0: usb2phy@e450 {

      compatible = "rockchip,rk3399-usb2phy";

      reg = <0xe450 0x10>;

      clocks = <&cru SCLK_USB2PHY0_REF>;

      clock-names = "phyclk";

      clock-output-names = "clk_usbphy0_480m";

      #clock-cells = <0>;

      #phy-cells = <0>;



      u2phy0_host: host-port {

        #phy-cells = <0>;

        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;

        interrupt-names = "linestate";

        #phy-cells = <0>;

      };



      u2phy0_otg: otg-port {

        #phy-cells = <0>;

        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;

        interrupt-names = "otg-bvalid", "otg-id", "linestate";

        #phy-cells = <0>;

      };

    };