Commit 07816e81 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Tweak the read latency fixup code 



If WM0 latency is zero we need to bump it (and the WM1+ latencies)
but a fixed amount. But any WM1+ level with zero latency must
not be touched since that indicates that corresponding WM level
isn't supported.

Currently the loop doing that adjustment does work, but only because
the previous loop modified the num_levels used as the loop boundary.
This all seems a bit too fragile. Remove the num_levels adjustment
and instead adjust the read latency loop to abort when it encounters
a zero latency value.

Reviewed-by: default avatarLuca Coelho <luciano.coelho@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250919193000.17665-4-ville.syrjala@linux.intel.com
parent 8ebb8e1a

drivers/gpu/drm/i915/display/skl_watermark.c

+7 −3
Original line number Diff line number Diff line
@@ -3198,8 +3198,6 @@ adjust_wm_latency(struct intel_display *display, 
		if (wm[level] == 0) {

			for (i = level + 1; i < num_levels; i++)

				wm[i] = 0;



			num_levels = level;

			break;

		}

	}
@@ -3212,9 +3210,15 @@ adjust_wm_latency(struct intel_display *display, 
	 * from the punit when level 0 response data is 0us.

	 */

	if (wm[0] == 0) {

		for (level = 0; level < num_levels; level++)

		wm[0] += read_latency;



		for (level = 1; level < num_levels; level++) {

			if (wm[level] == 0)

				break;



			wm[level] += read_latency;

		}

	}



	/*

	 * WA Level-0 adjustment for 16Gb+ DIMMs: SKL+