Commit 07a13f91 authored by John Smith's avatar John Smith Committed by Alex Deucher
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drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Fiji 



Previously this was initialized with zero which represented PCIe Gen
1.0 instead of using the
maximum value from the speed table which is the behaviour of all other
smumgr implementations.

Fixes: 18edef19 ("drm/amd/powerplay: implement fw image related smu interface for Fiji.")
Signed-off-by: default avatarJohn Smith <itistotalbotnet@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit c52238c9)
parent 238d468d

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

+1 −1
Original line number Diff line number Diff line
@@ -2024,7 +2024,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr) 
	table->VoltageResponseTime = 0;

	table->PhaseResponseTime = 0;

	table->MemoryThermThrottleEnable = 1;

	table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/

	table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);

	table->PCIeGenInterval = 1;

	table->VRConfig = 0;