Commit 0844947c authored by Deren Wu's avatar Deren Wu Committed by Felix Fietkau
Browse files

wifi: mt76: mt7925: update PCIe DMA settings 



Fix the wrong WFDMA settings to improve TX performance.

Fixes: c948b5da ("wifi: mt76: mt7925: add Mediatek Wi-Fi7 driver for mt7925 chips")
Signed-off-by: default avatarDeren Wu <deren.wu@mediatek.com>
Signed-off-by: default avatarMing Yen Hsieh <mingyen.hsieh@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 8536ef0a

drivers/net/wireless/mediatek/mt76/mt792x_dma.c

+10 −3
Original line number Diff line number Diff line
@@ -123,14 +123,13 @@ static void mt792x_dma_prefetch(struct mt792x_dev *dev) 


int mt792x_dma_enable(struct mt792x_dev *dev)

{

	if (is_mt7925(&dev->mt76))

		mt76_rmw(dev, MT_UWFDMA0_GLO_CFG_EXT1, BIT(28), BIT(28));



	/* configure perfetch settings */

	mt792x_dma_prefetch(dev);



	/* reset dma idx */

	mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);

	if (is_mt7925(&dev->mt76))

		mt76_wr(dev, MT_WFDMA0_RST_DRX_PTR, ~0);



	/* configure delay interrupt */

	mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
@@ -140,12 +139,20 @@ int mt792x_dma_enable(struct mt792x_dev *dev) 
		 MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |

		 MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |

		 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |

		 FIELD_PREP(MT_WFDMA0_GLO_CFG_DMA_SIZE, 3) |

		 MT_WFDMA0_GLO_CFG_FIFO_DIS_CHECK |

		 MT_WFDMA0_GLO_CFG_RX_WB_DDONE |

		 MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |

		 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);



	mt76_set(dev, MT_WFDMA0_GLO_CFG,

		 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);



	if (is_mt7925(&dev->mt76)) {

		mt76_rmw(dev, MT_UWFDMA0_GLO_CFG_EXT1, BIT(28), BIT(28));

		mt76_set(dev, MT_WFDMA0_INT_RX_PRI, 0x0F00);

		mt76_set(dev, MT_WFDMA0_INT_TX_PRI, 0x7F00);

	}

	mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT);



	/* enable interrupts for TX/RX rings */

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

+5 −0
Original line number Diff line number Diff line
@@ -292,9 +292,12 @@ 
#define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY	BIT(1)

#define MT_WFDMA0_GLO_CFG_RX_DMA_EN	BIT(2)

#define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY	BIT(3)

#define MT_WFDMA0_GLO_CFG_DMA_SIZE	GENMASK(5, 4)

#define MT_WFDMA0_GLO_CFG_TX_WB_DDONE	BIT(6)

#define MT_WFDMA0_GLO_CFG_FW_DWLD_BYPASS_DMASHDL BIT(9)

#define MT_WFDMA0_GLO_CFG_FIFO_DIS_CHECK	BIT(11)

#define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN	BIT(12)

#define MT_WFDMA0_GLO_CFG_RX_WB_DDONE	BIT(13)

#define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15)

#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2	BIT(21)

#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO	BIT(27)
@@ -322,6 +325,8 @@ 


#define MT_WFDMA0_RST_DTX_PTR		MT_WFDMA0(0x20c)

#define MT_WFDMA0_RST_DRX_PTR		MT_WFDMA0(0x280)

#define MT_WFDMA0_INT_RX_PRI		MT_WFDMA0(0x298)

#define MT_WFDMA0_INT_TX_PRI		MT_WFDMA0(0x29c)

#define MT_WFDMA0_GLO_CFG_EXT0		MT_WFDMA0(0x2b0)

#define MT_WFDMA0_CSR_TX_DMASHDL_ENABLE	BIT(6)

#define MT_WFDMA0_PRI_DLY_INT_CFG0	MT_WFDMA0(0x2f0)