Commit 086ed1d5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'exynos-drm-next-for-v6.13' of... 

Merge tag 'exynos-drm-next-for-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos

 into drm-next

New feature
- Add Decon driver support for Exynos7870 SoC
  . This patch adds driver data and support for Exynos7870 SoC
    in the Exynos7 Decon driver

Bug fixups for exynos7_drm_decon.c module
- Properly clear channels during bind
  . This patch implements shadow protection/unprotection to clear
    DECON channels properly, preventing kernel panic
- Fix ideal_clk by converting it to HZ
  . This patch corrects the clkdiv values by converting ideal_clk to Hz
    for consistency
- Fix uninitialized crtc reference in functions
  . This patch modifies functions to accept a pointer to
    the decon_context struct to avoid uninitialized references

Cleanups
- Remove unused prototype for crtc
  . This patch removes unused prototypes
      exynos_drm_crtc_wait_pending_update
      exynos_drm_crtc_finish_update
- And just typo fixup

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Inki Dae <inki.dae@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241104031341.36549-1-inki.dae@samsung.com
parents fb6c5b1f 53f4b30b

drivers/gpu/drm/exynos/exynos7_drm_decon.c

+79 −43
Original line number Diff line number Diff line
@@ -37,6 +37,24 @@ 


#define WINDOWS_NR	2



struct decon_data {

	unsigned int vidw_buf_start_base;

	unsigned int shadowcon_win_protect_shift;

	unsigned int wincon_burstlen_shift;

};



static struct decon_data exynos7_decon_data = {

	.vidw_buf_start_base = 0x80,

	.shadowcon_win_protect_shift = 10,

	.wincon_burstlen_shift = 11,

};



static struct decon_data exynos7870_decon_data = {

	.vidw_buf_start_base = 0x880,

	.shadowcon_win_protect_shift = 8,

	.wincon_burstlen_shift = 10,

};



struct decon_context {

	struct device			*dev;

	struct drm_device		*drm_dev;
@@ -55,11 +73,19 @@ struct decon_context { 
	wait_queue_head_t		wait_vsync_queue;

	atomic_t			wait_vsync_event;



	const struct decon_data *data;

	struct drm_encoder *encoder;

};



static const struct of_device_id decon_driver_dt_match[] = {

	{.compatible = "samsung,exynos7-decon"},

	{

		.compatible = "samsung,exynos7-decon",

		.data = &exynos7_decon_data,

	},

	{

		.compatible = "samsung,exynos7870-decon",

		.data = &exynos7870_decon_data,

	},

	{},

};

MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
@@ -81,10 +107,31 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 
	DRM_PLANE_TYPE_CURSOR,

};



static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)

/**

 * decon_shadow_protect_win() - disable updating values from shadow registers at vsync

 *

 * @ctx: display and enhancement controller context

 * @win: window to protect registers for

 * @protect: 1 to protect (disable updates)

 */

static void decon_shadow_protect_win(struct decon_context *ctx,

				     unsigned int win, bool protect)

{

	struct decon_context *ctx = crtc->ctx;

	u32 bits, val;

	unsigned int shift = ctx->data->shadowcon_win_protect_shift;



	bits = SHADOWCON_WINx_PROTECT(shift, win);



	val = readl(ctx->regs + SHADOWCON);

	if (protect)

		val |= bits;

	else

		val &= ~bits;

	writel(val, ctx->regs + SHADOWCON);

}



static void decon_wait_for_vblank(struct decon_context *ctx)

{

	if (ctx->suspended)

		return;
@@ -100,25 +147,33 @@ static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 
		DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");

}



static void decon_clear_channels(struct exynos_drm_crtc *crtc)

static void decon_clear_channels(struct decon_context *ctx)

{

	struct decon_context *ctx = crtc->ctx;

	unsigned int win, ch_enabled = 0;

	u32 val;



	/* Check if any channel is enabled. */

	for (win = 0; win < WINDOWS_NR; win++) {

		u32 val = readl(ctx->regs + WINCON(win));

		val = readl(ctx->regs + WINCON(win));



		if (val & WINCONx_ENWIN) {

			decon_shadow_protect_win(ctx, win, true);



			val &= ~WINCONx_ENWIN;

			writel(val, ctx->regs + WINCON(win));

			ch_enabled = 1;



			decon_shadow_protect_win(ctx, win, false);

		}

	}



	val = readl(ctx->regs + DECON_UPDATE);

	val |= DECON_UPDATE_STANDALONE_F;

	writel(val, ctx->regs + DECON_UPDATE);



	/* Wait for vsync, as disable channel takes effect at next vsync */

	if (ch_enabled)

		decon_wait_for_vblank(ctx->crtc);

		decon_wait_for_vblank(ctx);

}



static int decon_ctx_initialize(struct decon_context *ctx,
@@ -126,7 +181,7 @@ static int decon_ctx_initialize(struct decon_context *ctx, 
{

	ctx->drm_dev = drm_dev;



	decon_clear_channels(ctx->crtc);

	decon_clear_channels(ctx);



	return exynos_drm_register_dma(drm_dev, ctx->dev, &ctx->dma_priv);

}
@@ -140,7 +195,7 @@ static void decon_ctx_remove(struct decon_context *ctx) 
static u32 decon_calc_clkdiv(struct decon_context *ctx,

		const struct drm_display_mode *mode)

{

	unsigned long ideal_clk = mode->clock;

	unsigned long ideal_clk = mode->clock * 1000;

	u32 clkdiv;



	/* Find the clock divider value that gets us closest to ideal_clk */
@@ -263,6 +318,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 
{

	unsigned long val;

	int padding;

	unsigned int shift = ctx->data->wincon_burstlen_shift;



	val = readl(ctx->regs + WINCON(win));

	val &= ~WINCONx_BPPMODE_MASK;
@@ -270,44 +326,44 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 
	switch (fb->format->format) {

	case DRM_FORMAT_RGB565:

		val |= WINCONx_BPPMODE_16BPP_565;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_XRGB8888:

		val |= WINCONx_BPPMODE_24BPP_xRGB;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_XBGR8888:

		val |= WINCONx_BPPMODE_24BPP_xBGR;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_RGBX8888:

		val |= WINCONx_BPPMODE_24BPP_RGBx;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_BGRX8888:

		val |= WINCONx_BPPMODE_24BPP_BGRx;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_ARGB8888:

		val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |

			WINCONx_ALPHA_SEL;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_ABGR8888:

		val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |

			WINCONx_ALPHA_SEL;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_RGBA8888:

		val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |

			WINCONx_ALPHA_SEL;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_BGRA8888:

	default:

		val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |

			WINCONx_ALPHA_SEL;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	}
@@ -323,8 +379,8 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 


	padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;

	if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {

		val &= ~WINCONx_BURSTLEN_MASK;

		val |= WINCONx_BURSTLEN_8WORD;

		val &= ~WINCONx_BURSTLEN_MASK(shift);

		val |= WINCONx_BURSTLEN_8WORD(shift);

	}



	writel(val, ctx->regs + WINCON(win));
@@ -343,28 +399,6 @@ static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 
	writel(keycon1, ctx->regs + WKEYCON1_BASE(win));

}



/**

 * decon_shadow_protect_win() - disable updating values from shadow registers at vsync

 *

 * @ctx: display and enhancement controller context

 * @win: window to protect registers for

 * @protect: 1 to protect (disable updates)

 */

static void decon_shadow_protect_win(struct decon_context *ctx,

				     unsigned int win, bool protect)

{

	u32 bits, val;



	bits = SHADOWCON_WINx_PROTECT(win);



	val = readl(ctx->regs + SHADOWCON);

	if (protect)

		val |= bits;

	else

		val &= ~bits;

	writel(val, ctx->regs + SHADOWCON);

}



static void decon_atomic_begin(struct exynos_drm_crtc *crtc)

{

	struct decon_context *ctx = crtc->ctx;
@@ -391,6 +425,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, 
	unsigned int win = plane->index;

	unsigned int cpp = fb->format->cpp[0];

	unsigned int pitch = fb->pitches[0];

	unsigned int vidw_addr0_base = ctx->data->vidw_buf_start_base;



	if (ctx->suspended)

		return;
@@ -407,7 +442,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, 


	/* buffer start address */

	val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);

	writel(val, ctx->regs + VIDW_BUF_START(win));

	writel(val, ctx->regs + VIDW_BUF_START(vidw_addr0_base, win));



	padding = (pitch / cpp) - fb->width;
@@ -689,6 +724,7 @@ static int decon_probe(struct platform_device *pdev) 


	ctx->dev = dev;

	ctx->suspended = true;

	ctx->data = of_device_get_match_data(dev);



	i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");

	if (i80_if_timings)

drivers/gpu/drm/exynos/exynos_drm_crtc.h

+0 −3
Original line number Diff line number Diff line
@@ -19,9 +19,6 @@ struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev, 
					enum exynos_drm_output_type out_type,

					const struct exynos_drm_crtc_ops *ops,

					void *context);

void exynos_drm_crtc_wait_pending_update(struct exynos_drm_crtc *exynos_crtc);

void exynos_drm_crtc_finish_update(struct exynos_drm_crtc *exynos_crtc,

				   struct exynos_drm_plane *exynos_plane);



/* This function gets crtc device matched with out_type. */

struct exynos_drm_crtc *exynos_drm_crtc_get_by_type(struct drm_device *drm_dev,

drivers/gpu/drm/exynos/exynos_drm_gsc.c

+1 −1
Original line number Diff line number Diff line
@@ -1286,7 +1286,7 @@ static int gsc_probe(struct platform_device *pdev) 
		return ret;

	}



	/* context initailization */

	/* context initialization */

	ctx->id = pdev->id;



	platform_set_drvdata(pdev, ctx);

drivers/gpu/drm/exynos/regs-decon7.h

+7 −8
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ 
/* SHADOWCON */

#define SHADOWCON				0x30



#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))

#define SHADOWCON_WINx_PROTECT(_shf, _win)	(1 << ((_shf) + (_win)))



/* WINCONx */

#define WINCON(_win)				(0x50 + ((_win) * 4))
@@ -58,10 +58,9 @@ 
#define WINCONx_BUFSEL_SHIFT			28

#define WINCONx_TRIPLE_BUF_MODE			(0x1 << 18)

#define WINCONx_DOUBLE_BUF_MODE			(0x0 << 18)

#define WINCONx_BURSTLEN_16WORD			(0x0 << 11)

#define WINCONx_BURSTLEN_8WORD			(0x1 << 11)

#define WINCONx_BURSTLEN_MASK			(0x1 << 11)

#define WINCONx_BURSTLEN_SHIFT			11

#define WINCONx_BURSTLEN_16WORD(_shf)		(0x0 << (_shf))

#define WINCONx_BURSTLEN_8WORD(_shf)		(0x1 << (_shf))

#define WINCONx_BURSTLEN_MASK(_shf)		(0x1 << (_shf))

#define WINCONx_BLD_PLANE			(0 << 8)

#define WINCONx_BLD_PIX				(1 << 8)

#define WINCONx_ALPHA_MUL			(1 << 7)
@@ -89,9 +88,9 @@ 
#define VIDOSD_H(_x)				(0x80 + ((_x) * 4))



/* Frame buffer start addresses: VIDWxxADD0n */

#define VIDW_BUF_START(_win)			(0x80 + ((_win) * 0x10))

#define VIDW_BUF_START1(_win)			(0x84 + ((_win) * 0x10))

#define VIDW_BUF_START2(_win)			(0x88 + ((_win) * 0x10))

#define VIDW_BUF_START(_base, _win)		((_base) + ((_win) * 0x10))

#define VIDW_BUF_START1(_base, _win)		((_base) + ((_win) * 0x10))

#define VIDW_BUF_START2(_base, _win)		((_base) + ((_win) * 0x10))



#define VIDW_WHOLE_X(_win)			(0x0130 + ((_win) * 8))

#define VIDW_WHOLE_Y(_win)			(0x0134 + ((_win) * 8))