Commit 0883d63b authored by Caz Yokoyama's avatar Caz Yokoyama Committed by Lucas De Marchi
Browse files

drm/i915/adl_s: Add ADL-S platform info and PCI ids



- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been
  removed from ADLS. Disable PSR2 till we enable software/
  manual tracking.

v2:
- Add support for different ADLS SOC steppings to select
  correct GT/DISP stepping based on Bspec 53655 based on
  feedback from Matt Roper.(aswarup)

v3:
- Make display/gt steppings info generic for reuse with TGL and ADLS.
- Modify the macros to reuse tgl_revids_get()
- Add HTI support to adls device info.(mdroper)

v4:
- Rebase on TGL patch for applying WAs based on stepping info from
  Matt Roper's feedback.(aswarup)

v5:
- Replace macros with PCI IDs in revid to stepping table.

v6: remove stray adls_revids (Lucas)

Bspec: 53597
Bspec: 53648
Bspec: 53655
Bspec: 48028
Bspec: 53650
BSpec: 50422

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarCaz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: default avatarAditya Swarup <aditya.swarup@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210119192931.1116500-2-lucas.demarchi@intel.com
parent 7e6c064e
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+8 −0
Original line number Diff line number Diff line
@@ -84,6 +84,14 @@ const struct i915_rev_steppings tgl_revid_step_tbl[] = {
	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
};

const struct i915_rev_steppings adls_revid_step_tbl[] = {
	[0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
	[0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
	[0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
	[0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
	[0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
};

static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
{
	wal->name = name;
+24 −1
Original line number Diff line number Diff line
@@ -1417,6 +1417,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
#define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1560,6 +1561,7 @@ extern const struct i915_rev_steppings kbl_revids[];

enum {
	STEP_A0,
	STEP_A2,
	STEP_B0,
	STEP_B1,
	STEP_C0,
@@ -1568,9 +1570,11 @@ enum {

#define TGL_UY_REVID_STEP_TBL_SIZE	4
#define TGL_REVID_STEP_TBL_SIZE		2
#define ADLS_REVID_STEP_TBL_SIZE	13

extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];

static inline const struct i915_rev_steppings *
tgl_stepping_get(struct drm_i915_private *dev_priv)
@@ -1579,7 +1583,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
	u8 size;
	const struct i915_rev_steppings *revid_step_tbl;

	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
	if (IS_ALDERLAKE_S(dev_priv)) {
		revid_step_tbl = adls_revid_step_tbl;
		size = ARRAY_SIZE(adls_revid_step_tbl);
	} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
		revid_step_tbl = tgl_uy_revid_step_tbl;
		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
	} else {
@@ -1621,6 +1628,22 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
#define IS_DG1_REVID(p, since, until) \
	(IS_DG1(p) && IS_REVID(p, since, until))

#define ADLS_REVID_A0		0x0
#define ADLS_REVID_A2		0x1
#define ADLS_REVID_B0		0x4
#define ADLS_REVID_G0		0x8
#define ADLS_REVID_C0		0xC /*Same as H0 ADLS SOC stepping*/

#define IS_ADLS_DISP_STEPPING(p, since, until) \
	(IS_ALDERLAKE_S(p) && \
	 tgl_stepping_get(p)->disp_stepping >= (since) && \
	 tgl_stepping_get(p)->disp_stepping <= (until))

#define IS_ADLS_GT_STEPPING(p, since, until) \
	(IS_ALDERLAKE_S(p) && \
	 tgl_stepping_get(p)->gt_stepping >= (since) && \
	 tgl_stepping_get(p)->gt_stepping <= (until))

#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
+13 −0
Original line number Diff line number Diff line
@@ -923,6 +923,18 @@ static const struct intel_device_info dg1_info __maybe_unused = {
	.ppgtt_size = 47,
};

static const struct intel_device_info adl_s_info = {
	GEN12_FEATURES,
	PLATFORM(INTEL_ALDERLAKE_S),
	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
	.require_force_probe = 1,
	.display.has_hti = 1,
	.display.has_psr_hw_tracking = 0,
	.platform_engine_mask =
		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
	.dma_mask_size = 46,
};

#undef GEN
#undef PLATFORM

@@ -999,6 +1011,7 @@ static const struct pci_device_id pciidlist[] = {
	INTEL_JSL_IDS(&jsl_info),
	INTEL_TGL_12_IDS(&tgl_info),
	INTEL_RKL_IDS(&rkl_info),
	INTEL_ADLS_IDS(&adl_s_info),
	{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ static const char * const platform_names[] = {
	PLATFORM_NAME(TIGERLAKE),
	PLATFORM_NAME(ROCKETLAKE),
	PLATFORM_NAME(DG1),
	PLATFORM_NAME(ALDERLAKE_S),
};
#undef PLATFORM_NAME

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ enum intel_platform {
	INTEL_TIGERLAKE,
	INTEL_ROCKETLAKE,
	INTEL_DG1,
	INTEL_ALDERLAKE_S,
	INTEL_MAX_PLATFORMS
};

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