Commit 08a01ec3 authored by Nicholas Carbones's avatar Nicholas Carbones Committed by Alex Deucher
Browse files

drm/amd/display: Add Gfx Base Case For Linear Tiling Handling 



[Why]
Post-driver cases always use linear tiling yet there is no dedicated
Gfx handling for this condition.

[How]
Add DcGfxBase/DalGfxBase to gfx version enums and set tiling to linear
when it is used. Also, enforce the use of proper tiling format as tiling
information is used.

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarNicholas Carbones <ncarbone@amd.com>
Signed-off-by: default avatarWayne Lin <wayne.lin@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d6bd606

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −0
Original line number Diff line number Diff line
@@ -8032,6 +8032,7 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc, 
	dc_plane_state->plane_size.chroma_size.height  = stream->src.height;

	dc_plane_state->plane_size.chroma_size.width   = stream->src.width;

	dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;

	dc_plane_state->tiling_info.gfxversion = DcGfxVersion9;

	dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;

	dc_plane_state->rotation = ROTATION_ANGLE_0;

	dc_plane_state->is_tiling_rotated = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −0
Original line number Diff line number Diff line
@@ -2768,6 +2768,7 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct 
		case DcGfxVersion7:

		case DcGfxVersion8:

		case DcGfxVersionUnknown:

		case DcGfxBase:

		default:

			break;

		}

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

+7 −0
Original line number Diff line number Diff line
@@ -2065,6 +2065,13 @@ void get_surface_tile_visual_confirm_color( 
	while (bottom_pipe_ctx->bottom_pipe != NULL)

		bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;



	if (bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxBase) {

		/* LINEAR Surface - set border color to red */

		color->color_r_cr = color_value;

		return;

	}



	ASSERT(bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9);

	switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {

	case DC_SW_LINEAR:

		/* LINEAR Surface - set border color to red */

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -4434,6 +4434,7 @@ enum dc_status dc_validate_global_state( 


			if (dc->res_pool->funcs->patch_unknown_plane_state &&

					pipe_ctx->plane_state &&

					pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9 &&

					pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {

				result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

				if (result != DC_OK)

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+2 −1
Original line number Diff line number Diff line
@@ -342,7 +342,8 @@ enum swizzle_mode_addr3_values { 
};



enum dc_gfxversion {

	DcGfxVersion7 = 0,

	DcGfxBase = 0,

	DcGfxVersion7,

	DcGfxVersion8,

	DcGfxVersion9,

	DcGfxVersion10,