Commit 08e95044 authored by Tomer Maimon's avatar Tomer Maimon Committed by Arnd Bergmann
Browse files

dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock 



Add binding for the Arbel BMC NPCM8XX Clock controller.

Signed-off-by: default avatarTomer Maimon <tmaimon77@gmail.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 5e1f5ea3

Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Nuvoton NPCM8XX Clock Controller Binding



maintainers:

  - Tomer Maimon <tmaimon77@gmail.com>



description: |

  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which

  generates and supplies clocks to all modules within the BMC.



properties:

  compatible:

    enum:

      - nuvoton,npcm845-clk



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1

    description:

      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full

      list of NPCM8XX clock IDs.



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    ahb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@f0801000 {

            compatible = "nuvoton,npcm845-clk";

            reg = <0x0 0xf0801000 0x0 0x1000>;

            #clock-cells = <1>;

        };

    };

...

include/dt-bindings/clock/nuvoton,npcm845-clk.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (C) 2021 Nuvoton Technologies.

 * Author: Tomer Maimon <tomer.maimon@nuvoton.com>

 *

 * Device Tree binding constants for NPCM8XX clock controller.

 */



#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H

#define __DT_BINDINGS_CLOCK_NPCM8XX_H



#define NPCM8XX_CLK_CPU		0

#define NPCM8XX_CLK_GFX_PIXEL	1

#define NPCM8XX_CLK_MC		2

#define NPCM8XX_CLK_ADC		3

#define NPCM8XX_CLK_AHB		4

#define NPCM8XX_CLK_TIMER	5

#define NPCM8XX_CLK_UART	6

#define NPCM8XX_CLK_UART2	7

#define NPCM8XX_CLK_MMC		8

#define NPCM8XX_CLK_SPI3	9

#define NPCM8XX_CLK_PCI		10

#define NPCM8XX_CLK_AXI		11

#define NPCM8XX_CLK_APB4	12

#define NPCM8XX_CLK_APB3	13

#define NPCM8XX_CLK_APB2	14

#define NPCM8XX_CLK_APB1	15

#define NPCM8XX_CLK_APB5	16

#define NPCM8XX_CLK_CLKOUT	17

#define NPCM8XX_CLK_GFX		18

#define NPCM8XX_CLK_SU		19

#define NPCM8XX_CLK_SU48	20

#define NPCM8XX_CLK_SDHC	21

#define NPCM8XX_CLK_SPI0	22

#define NPCM8XX_CLK_SPI1	23

#define NPCM8XX_CLK_SPIX	24

#define NPCM8XX_CLK_RG		25

#define NPCM8XX_CLK_RCP		26

#define NPCM8XX_CLK_PRE_ADC	27

#define NPCM8XX_CLK_ATB		28

#define NPCM8XX_CLK_PRE_CLK	29

#define NPCM8XX_CLK_TH		30

#define NPCM8XX_CLK_REFCLK	31

#define NPCM8XX_CLK_SYSBYPCK	32

#define NPCM8XX_CLK_MCBYPCK	33



#define NPCM8XX_NUM_CLOCKS	(NPCM8XX_CLK_MCBYPCK + 1)



#endif