Unverified Commit 091ffb00 authored by Matt Coster's avatar Matt Coster
Browse files

drm/imagination: Rename event_mask -> status_mask 



Now that enable_reg isn't used, rename the previously shared event_mask to
status_mask since it's only used with status_reg.

Reviewed-by: default avatarFrank Binns <frank.binns@imgtec.com>
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-9-eda620c5865f@imgtec.com


Signed-off-by: default avatarMatt Coster <matt.coster@imgtec.com>
parent 2c08b725

drivers/gpu/drm/imagination/pvr_fw.h

+3 −3
Original line number Diff line number Diff line
@@ -199,8 +199,8 @@ struct pvr_fw_defs { 
		 */

		u32 clear_reg;



		/** @event_mask: Bitmask of events to listen for in the status_reg. */

		u32 event_mask;

		/** @status_mask: Bitmask of events to listen for in the status_reg. */

		u32 status_mask;



		/** @clear_mask: Value to write to the clear_reg in order to clear FW IRQs. */

		u32 clear_mask;
@@ -404,7 +404,7 @@ struct pvr_fw_device { 
	pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value)



#define pvr_fw_irq_pending(pvr_dev) \

	(pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.event_mask)

	(pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.status_mask)



#define pvr_fw_irq_clear(pvr_dev) \

	pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_mask)

drivers/gpu/drm/imagination/pvr_fw_meta.c

+1 −1
Original line number Diff line number Diff line
@@ -549,7 +549,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta = { 
	.irq = {

		.status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS,

		.clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS,

		.event_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN,

		.status_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN,

		.clear_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK,

	},

};

drivers/gpu/drm/imagination/pvr_fw_mips.c

+1 −1
Original line number Diff line number Diff line
@@ -243,7 +243,7 @@ const struct pvr_fw_defs pvr_fw_defs_mips = { 
	.irq = {

		.status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS,

		.clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR,

		.event_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN,

		.status_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN,

		.clear_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN,

	},

};