Commit 0a1f6dd7 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.15-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Fix mmc A clock gate definition on Amlogic g12 SoCs
 - Properly set cpu cluster A on Amlogic g12b
 - Fix 32k clock definition on Amlogic gxbb
 - Correct documentation typo on Amlogic a1

* tag 'clk-meson-v6.15-1' of https://github.com/BayLibre/clk-meson:
  clk: amlogic: a1: fix a typo
  clk: amlogic: gxbb: drop non existing 32k clock parent
  clk: amlogic: gxbb: drop incorrect flag on 32k clock
  clk: amlogic: g12b: fix cluster A parent data
  clk: amlogic: g12a: fix mmc A peripheral clock
parents 2014c95a b3c221e7

drivers/clk/meson/a1-pll.c

+1 −1
Original line number Diff line number Diff line
@@ -356,7 +356,7 @@ static struct platform_driver a1_pll_clkc_driver = { 
};

module_platform_driver(a1_pll_clkc_driver);



MODULE_DESCRIPTION("Amlogic S4 PLL Clock Controller driver");

MODULE_DESCRIPTION("Amlogic A1 PLL Clock Controller driver");

MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");

MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");

MODULE_LICENSE("GPL");

drivers/clk/meson/g12a.c

+25 −13
Original line number Diff line number Diff line
@@ -1137,8 +1137,18 @@ static struct clk_regmap g12a_cpu_clk_div16_en = { 
	.hw.init = &(struct clk_init_data) {

		.name = "cpu_clk_div16_en",

		.ops = &clk_regmap_gate_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cpu_clk.hw

		.parent_data = &(const struct clk_parent_data) {

			/*

			 * Note:

			 * G12A and G12B have different cpu clocks (with

			 * different struct clk_hw). We fallback to the global

			 * naming string mechanism so this clock picks

			 * up the appropriate one. Same goes for the other

			 * clock using cpu cluster A clock output and present

			 * on both G12 variant.

			 */

			.name = "cpu_clk",

			.index = -1,

		},

		.num_parents = 1,

		/*
@@ -1203,7 +1213,10 @@ static struct clk_regmap g12a_cpu_clk_apb_div = { 
	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_apb_div",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },

		.parent_data = &(const struct clk_parent_data) {

			.name = "cpu_clk",

			.index = -1,

		},

		.num_parents = 1,

	},

};
@@ -1237,7 +1250,10 @@ static struct clk_regmap g12a_cpu_clk_atb_div = { 
	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_atb_div",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },

		.parent_data = &(const struct clk_parent_data) {

			.name = "cpu_clk",

			.index = -1,

		},

		.num_parents = 1,

	},

};
@@ -1271,7 +1287,10 @@ static struct clk_regmap g12a_cpu_clk_axi_div = { 
	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_axi_div",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },

		.parent_data = &(const struct clk_parent_data) {

			.name = "cpu_clk",

			.index = -1,

		},

		.num_parents = 1,

	},

};
@@ -1306,13 +1325,6 @@ static struct clk_regmap g12a_cpu_clk_trace_div = { 
		.name = "cpu_clk_trace_div",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_data = &(const struct clk_parent_data) {

			/*

			 * Note:

			 * G12A and G12B have different cpu_clks (with

			 * different struct clk_hw). We fallback to the global

			 * naming string mechanism so cpu_clk_trace_div picks

			 * up the appropriate one.

			 */

			.name = "cpu_clk",

			.index = -1,

		},
@@ -4311,7 +4323,7 @@ static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14); 
static MESON_GATE(g12a_hiu_reg,			HHI_GCLK_MPEG0,	19);

static MESON_GATE(g12a_mipi_dsi_phy,		HHI_GCLK_MPEG0,	20);

static MESON_GATE(g12a_assist_misc,		HHI_GCLK_MPEG0,	23);

static MESON_GATE(g12a_emmc_a,			HHI_GCLK_MPEG0,	4);

static MESON_GATE(g12a_emmc_a,			HHI_GCLK_MPEG0,	24);

static MESON_GATE(g12a_emmc_b,			HHI_GCLK_MPEG0,	25);

static MESON_GATE(g12a_emmc_c,			HHI_GCLK_MPEG0,	26);

static MESON_GATE(g12a_audio_codec,		HHI_GCLK_MPEG0,	28);

drivers/clk/meson/gxbb.c

+7 −7
Original line number Diff line number Diff line
@@ -1266,14 +1266,13 @@ static struct clk_regmap gxbb_cts_i958 = { 
	},

};



static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {

	{ .fw_name = "xtal", },

/*

	 * FIXME: This clock is provided by the ao clock controller but the

	 * clock is not yet part of the binding of this controller, so string

	 * name must be use to set this parent.

 * This table skips a clock named 'cts_slow_oscin' in the documentation

 * This clock does not exist yet in this controller or the AO one

 */

	{ .name = "cts_slow_oscin", .index = -1 },

static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 };

static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {

	{ .fw_name = "xtal", },

	{ .hw = &gxbb_fclk_div3.hw },

	{ .hw = &gxbb_fclk_div5.hw },

};
@@ -1283,6 +1282,7 @@ static struct clk_regmap gxbb_32k_clk_sel = { 
		.offset = HHI_32K_CLK_CNTL,

		.mask = 0x3,

		.shift = 16,

		.table = gxbb_32k_clk_parents_val_table,

		},

	.hw.init = &(struct clk_init_data){

		.name = "32k_clk_sel",
@@ -1306,7 +1306,7 @@ static struct clk_regmap gxbb_32k_clk_div = { 
			&gxbb_32k_clk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,

		.flags = CLK_SET_RATE_PARENT,

	},

};