Commit 0acd1693 authored by Neil Armstrong's avatar Neil Armstrong Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8550: add OPP table support to PCIe 



The PCIe bus interconnect path can be scaled depending on the
PCIe link established, add the OPP table with all the possible
link speeds and the associated power domain level.

Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-3-eaa8b10e2af7@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 48c84d96

arch/arm64/boot/dts/qcom/sm8550.dtsi

+89 −0
Original line number Diff line number Diff line
@@ -1897,8 +1897,49 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 
			phys = <&pcie0_phy>;

			phy-names = "pciephy";



			operating-points-v2 = <&pcie0_opp_table>;



			status = "disabled";



			pcie0_opp_table: opp-table {

				compatible = "operating-points-v2";



				/* GEN 1 x1 */

				opp-2500000 {

					opp-hz = /bits/ 64 <2500000>;

					required-opps = <&rpmhpd_opp_low_svs>;

					opp-peak-kBps = <250000 1>;

				};



				/* GEN 1 x2 and GEN 2 x1 */

				opp-5000000 {

					opp-hz = /bits/ 64 <5000000>;

					required-opps = <&rpmhpd_opp_low_svs>;

					opp-peak-kBps = <500000 1>;

				};



				/* GEN 2 x2 */

				opp-10000000 {

					opp-hz = /bits/ 64 <10000000>;

					required-opps = <&rpmhpd_opp_low_svs>;

					opp-peak-kBps = <1000000 1>;

				};



				/* GEN 3 x1 */

				opp-8000000 {

					opp-hz = /bits/ 64 <8000000>;

					required-opps = <&rpmhpd_opp_nom>;

					opp-peak-kBps = <984500 1>;

				};



				/* GEN 3 x2 */

				opp-16000000 {

					opp-hz = /bits/ 64 <16000000>;

					required-opps = <&rpmhpd_opp_nom>;

					opp-peak-kBps = <1969000 1>;

				};

			};



			pcieport0: pcie@0 {

				device_type = "pci";

				reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -2023,8 +2064,56 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 
			phys = <&pcie1_phy>;

			phy-names = "pciephy";



			operating-points-v2 = <&pcie1_opp_table>;



			status = "disabled";



			pcie1_opp_table: opp-table {

				compatible = "operating-points-v2";



				/* GEN 1 x1 */

				opp-2500000 {

					opp-hz = /bits/ 64 <2500000>;

					required-opps = <&rpmhpd_opp_low_svs>;

					opp-peak-kBps = <250000 1>;

				};



				/* GEN 1 x2 and GEN 2 x1 */

				opp-5000000 {

					opp-hz = /bits/ 64 <5000000>;

					required-opps = <&rpmhpd_opp_low_svs>;

					opp-peak-kBps = <500000 1>;

				};



				/* GEN 2 x2 */

				opp-10000000 {

					opp-hz = /bits/ 64 <10000000>;

					required-opps = <&rpmhpd_opp_low_svs>;

					opp-peak-kBps = <1000000 1>;

				};



				/* GEN 3 x1 */

				opp-8000000 {

					opp-hz = /bits/ 64 <8000000>;

					required-opps = <&rpmhpd_opp_nom>;

					opp-peak-kBps = <984500 1>;

				};



				/* GEN 3 x2 and GEN 4 x1 */

				opp-16000000 {

					opp-hz = /bits/ 64 <16000000>;

					required-opps = <&rpmhpd_opp_nom>;

					opp-peak-kBps = <1969000 1>;

				};



				/* GEN 4 x2 */

				opp-32000000 {

					opp-hz = /bits/ 64 <32000000>;

					required-opps = <&rpmhpd_opp_nom>;

					opp-peak-kBps = <3938000 1>;

				};

			};



			pcie@0 {

				device_type = "pci";

				reg = <0x0 0x0 0x0 0x0 0x0>;