Commit 0afcee10 authored by Ivan Vecera's avatar Ivan Vecera Committed by Jakub Kicinski
Browse files

dt-bindings: dpll: Add DPLL device and pin 



Add a common DT schema for DPLL device and its associated pins.
The DPLL (device phase-locked loop) is a device used for precise clock
synchronization in networking and telecom hardware.

The device includes one or more DPLLs (channels) and one or more
physical input/output pins.

Each DPLL channel is used either to provide a pulse-per-clock signal or
to drive an Ethernet equipment clock.

The input and output pins have the following properties:
* label: specifies board label
* connection type: specifies its usage depending on wiring
* list of supported or allowed frequencies: depending on how the pin
  is connected and where)
* embedded sync capability: indicates whether the pin supports this

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarIvan Vecera <ivecera@redhat.com>
Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
Link: https://patch.msgid.link/20250704182202.1641943-2-ivecera@redhat.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent f47e8f61

Documentation/devicetree/bindings/dpll/dpll-device.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dpll/dpll-device.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Digital Phase-Locked Loop (DPLL) Device



maintainers:

  - Ivan Vecera <ivecera@redhat.com>



description:

  Digital Phase-Locked Loop (DPLL) device is used for precise clock

  synchronization in networking and telecom hardware. The device can

  have one or more channels (DPLLs) and one or more physical input and

  output pins. Each DPLL channel can either produce pulse-per-clock signal

  or drive ethernet equipment clock. The type of each channel can be

  indicated by dpll-types property.



properties:

  $nodename:

    pattern: "^dpll(@.*)?$"



  "#address-cells":

    const: 0



  "#size-cells":

    const: 0



  dpll-types:

    description: List of DPLL channel types, one per DPLL instance.

    $ref: /schemas/types.yaml#/definitions/non-unique-string-array

    items:

      enum: [pps, eec]



  input-pins:

    type: object

    description: DPLL input pins

    unevaluatedProperties: false



    properties:

      "#address-cells":

        const: 1

      "#size-cells":

        const: 0



    patternProperties:

      "^pin@[0-9a-f]+$":

        $ref: /schemas/dpll/dpll-pin.yaml

        unevaluatedProperties: false



    required:

      - "#address-cells"

      - "#size-cells"



  output-pins:

    type: object

    description: DPLL output pins

    unevaluatedProperties: false



    properties:

      "#address-cells":

        const: 1

      "#size-cells":

        const: 0



    patternProperties:

      "^pin@[0-9]+$":

        $ref: /schemas/dpll/dpll-pin.yaml

        unevaluatedProperties: false



    required:

      - "#address-cells"

      - "#size-cells"



additionalProperties: true

Documentation/devicetree/bindings/dpll/dpll-pin.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: DPLL Pin



maintainers:

  - Ivan Vecera <ivecera@redhat.com>



description: |

  The DPLL pin is either a physical input or output pin that is provided

  by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by

  its physical order number that is stored in reg property and can have

  an additional set of properties like supported (allowed) frequencies,

  label, type and may support embedded sync.



  Note that the pin in this context has nothing to do with pinctrl.



properties:

  reg:

    description: Hardware index of the DPLL pin.

    maxItems: 1



  connection-type:

    description: Connection type of the pin

    $ref: /schemas/types.yaml#/definitions/string

    enum: [ext, gnss, int, mux, synce]



  esync-control:

    description: Indicates whether the pin supports embedded sync functionality.

    type: boolean



  label:

    description: String exposed as the pin board label

    $ref: /schemas/types.yaml#/definitions/string



  supported-frequencies-hz:

    description: List of supported frequencies for this pin, expressed in Hz.



required:

  - reg



additionalProperties: false

MAINTAINERS

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Original line number Diff line number Diff line
@@ -7335,6 +7335,8 @@ M: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> 
M:	Jiri Pirko <jiri@resnulli.us>

L:	netdev@vger.kernel.org

S:	Supported

F:	Documentation/devicetree/bindings/dpll/dpll-device.yaml

F:	Documentation/devicetree/bindings/dpll/dpll-pin.yaml

F:	Documentation/driver-api/dpll.rst

F:	drivers/dpll/*

F:	include/linux/dpll.h