Commit 0bae0872 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable() 



Move the FP divider programming into ibx_pch_dpll_enable(). No reason
that I can see why these would have to be programmed this early.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-13-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 62d66b21

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+3 −10
Original line number Diff line number Diff line
@@ -451,15 +451,6 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, 
	return val & DPLL_VCO_ENABLE;

}



static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,

				 struct intel_shared_dpll *pll)

{

	const enum intel_dpll_id id = pll->info->id;



	intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0);

	intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1);

}



static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)

{

	u32 val;
@@ -481,6 +472,9 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, 
	/* PCH refclock must be enabled first */

	ibx_assert_pch_refclk_enabled(dev_priv);



	intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0);

	intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1);



	intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll);



	/* Wait for the clocks to stabilize. */
@@ -558,7 +552,6 @@ static void ibx_dump_hw_state(struct drm_i915_private *dev_priv, 
}



static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {

	.prepare = ibx_pch_dpll_prepare,

	.enable = ibx_pch_dpll_enable,

	.disable = ibx_pch_dpll_disable,

	.get_hw_state = ibx_pch_dpll_get_hw_state,