Commit 0c31f6a3 authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson
Browse files

clk: qcom: clk-alpha-pll: Add support for Regera PLL ops 



Regera PLL ops are required to control the Regera PLL from clock
controller drivers, hence add the Regera PLL ops and configure
function.

Signed-off-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Signed-off-by: default avatarSatya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240731062916.2680823-6-quic_skakitap@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent a689c296

drivers/clk/qcom/clk-alpha-pll.c

+31 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/kernel.h>
@@ -2657,3 +2657,33 @@ const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 
	.set_rate = clk_alpha_pll_stromer_plus_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);



void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config)

{

	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);

	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);



	/* Set operation mode to STANDBY */

	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);

}

EXPORT_SYMBOL_GPL(clk_regera_pll_configure);



const struct clk_ops clk_alpha_pll_regera_ops = {

	.enable = clk_zonda_pll_enable,

	.disable = clk_zonda_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_zonda_pll_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);

drivers/clk/qcom/clk-alpha-pll.h

+5 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ enum { 
	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,

	CLK_ALPHA_PLL_TYPE_AGERA,

	CLK_ALPHA_PLL_TYPE_ZONDA,

	CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,

	CLK_ALPHA_PLL_TYPE_ZONDA_OLE,

	CLK_ALPHA_PLL_TYPE_LUCID_EVO,

	CLK_ALPHA_PLL_TYPE_LUCID_OLE,
@@ -193,6 +194,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; 
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;

#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops



extern const struct clk_ops clk_alpha_pll_regera_ops;



void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);

void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -216,5 +219,7 @@ void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm 
				  const struct alpha_pll_config *config);

void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			       const struct alpha_pll_config *config);

void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);



#endif