Commit 0cdee263 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'media/v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media 

Pull media updates from Mauro Carvalho Chehab:

 - v4l2 core:
     - sub-device framework routing improvements
     - NV12M tiled variants added to v4l2_format_info
     - some fixes at control handler freeing logic
     - fixed H264 SEPARATE_COLOUR_PLANE check

 - new staging driver: Intel IPU7 PCI

 - Rockchip video decoder driver got promoted from staging

 - iris: added HEVC/VP9 encoder/decoder support

 - vsp1: driver has gained Renesas VSPX support

 - uvc:
     - switched to vb2 ioctl helpers
     - added MSXU 1.5 metadata support

 - atomisp: GC0310 sensor driver cleanups in preparation for moving it
   out of staging

 - Lots of cleanup, fixes and improvements

* tag 'media/v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (310 commits)
  media: rkvdec: Unstage the driver
  media: rkvdec: Remove TODO file
  media: dt-bindings: rockchip: Add RK3576 Video Decoder bindings
  media: dt-bindings: rockchip: Document RK3588 Video Decoder bindings
  media: amphion: Support dmabuf and v4l2 buffer without binding
  media: verisilicon: postproc: 4K support
  media: v4l2: Add support for NV12M tiled variants to v4l2_format_info()
  media: uvcvideo: Use a count variable for meta_formats instead of 0 terminating
  media: uvcvideo: Auto-set UVC_QUIRK_MSXU_META
  media: uvcvideo: Introduce V4L2_META_FMT_UVC_MSXU_1_5
  media: uvcvideo: Introduce dev->meta_formats
  media: Documentation: Add note about UVCH length field
  media: uvcvideo: Do not mark valid metadata as invalid
  media: uvcvideo: uvc_v4l2_unlocked_ioctl: Invert PM logic
  media: core: export v4l2_translate_cmd
  media: uvcvideo: Turn on the camera if V4L2_EVENT_SUB_FL_SEND_INITIAL
  media: uvcvideo: Remove stream->is_streaming field
  media: uvcvideo: Split uvc_stop_streaming()
  media: uvcvideo: Handle locks in uvc_queue_return_buffers
  media: uvcvideo: Use vb2 ioctl and fop helpers
  ...
parents 27152608 d968e50b

.mailmap

+3 −2
Original line number Diff line number Diff line
@@ -287,8 +287,9 @@ Gustavo Padovan <padovan@profusion.mobi> 
Hamza Mahfooz <hamzamahfooz@linux.microsoft.com> <hamza.mahfooz@amd.com>

Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>

Hans de Goede <hansg@kernel.org> <hdegoede@redhat.com>

Hans Verkuil <hverkuil@xs4all.nl> <hansverk@cisco.com>

Hans Verkuil <hverkuil@xs4all.nl> <hverkuil-cisco@xs4all.nl>

Hans Verkuil <hverkuil@kernel.org> <hverkuil@xs4all.nl>

Hans Verkuil <hverkuil@kernel.org> <hverkuil-cisco@xs4all.nl>

Hans Verkuil <hverkuil@kernel.org> <hansverk@cisco.com>

Harry Yoo <harry.yoo@oracle.com> <42.hyeyoo@gmail.com>

Heiko Carstens <hca@linux.ibm.com> <h.carstens@de.ibm.com>

Heiko Carstens <hca@linux.ibm.com> <heiko.carstens@de.ibm.com>

Documentation/devicetree/bindings/media/cdns,csi2rx.yaml

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@@ -24,6 +24,14 @@ properties: 
  reg:

    maxItems: 1



  interrupts:

    maxItems: 2



  interrupt-names:

    items:

      - const: error_irq

      - const: irq



  clocks:

    items:

      - description: CSI2Rx system clock

Documentation/devicetree/bindings/media/fsl,imx6q-vdoa.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/fsl,imx6q-vdoa.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale Video Data Order Adapter



description:

  The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose

  is to reorder video data from the macroblock tiled order produced by the CODA

  960 VPU to the conventional raster-scan order for scanout.



maintainers:

  - Frank Li <Frank.Li@nxp.com>



properties:

  compatible:

    const: "fsl,imx6q-vdoa"



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/imx6qdl-clock.h>



    vdoa@21e4000 {

        compatible = "fsl,imx6q-vdoa";

        reg = <0x021e4000 0x4000>;

        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clks IMX6QDL_CLK_VDOA>;

    };

Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: i.MX8QM Image Sensing Interface



maintainers:

  - Frank Li <Frank.Li@nxp.com>



description:

  The Image Sensing Interface (ISI) combines image processing pipelines with

  DMA engines to process and capture frames originating from a variety of

  sources. The inputs to the ISI go through Pixel Link interfaces, and their

  number and nature is SoC-dependent. They cover both capture interfaces (MIPI

  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.



properties:

  compatible:

    enum:

      - fsl,imx8qm-isi



  reg:

    maxItems: 1



  clocks:

    maxItems: 8



  clock-names:

    items:

      - const: per0

      - const: per1

      - const: per2

      - const: per3

      - const: per4

      - const: per5

      - const: per6

      - const: per7



  interrupts:

    maxItems: 8



  power-domains:

    maxItems: 8



  ports:

    $ref: /schemas/graph.yaml#/properties/ports

    properties:

      port@2:

        $ref: /schemas/graph.yaml#/properties/port

        description: MIPI CSI-2 RX 0

      port@3:

        $ref: /schemas/graph.yaml#/properties/port

        description: MIPI CSI-2 RX 1

      port@4:

        $ref: /schemas/graph.yaml#/properties/port

        description: HDMI RX



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts

  - power-domains

  - ports



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/imx8-clock.h>

    #include <dt-bindings/clock/imx8-lpcg.h>

    #include <dt-bindings/firmware/imx/rsrc.h>



    image-controller@58100000 {

        compatible = "fsl,imx8qm-isi";

        reg = <0x58100000 0x80000>;

        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,

                 <&pdma1_lpcg IMX_LPCG_CLK_0>,

                 <&pdma2_lpcg IMX_LPCG_CLK_0>,

                 <&pdma3_lpcg IMX_LPCG_CLK_0>,

                 <&pdma4_lpcg IMX_LPCG_CLK_0>,

                 <&pdma5_lpcg IMX_LPCG_CLK_0>,

                 <&pdma6_lpcg IMX_LPCG_CLK_0>,

                 <&pdma7_lpcg IMX_LPCG_CLK_0>;

        clock-names = "per0", "per1", "per2", "per3",

                      "per4", "per5", "per6", "per7";

        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,

                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,

                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>,

                        <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@2 {

                reg = <2>;

                endpoint {

                    remote-endpoint = <&mipi_csi0_out>;

                };

            };

        };

    };

...

Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: i.MX8QXP Image Sensing Interface



maintainers:

  - Frank Li <Frank.Li@nxp.com>



description:

  The Image Sensing Interface (ISI) combines image processing pipelines with

  DMA engines to process and capture frames originating from a variety of

  sources. The inputs to the ISI go through Pixel Link interfaces, and their

  number and nature is SoC-dependent. They cover both capture interfaces (MIPI

  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.



properties:

  compatible:

    enum:

      - fsl,imx8qxp-isi



  reg:

    maxItems: 1



  clocks:

    maxItems: 6



  clock-names:

    items:

      - const: per0

      - const: per1

      - const: per2

      - const: per3

      - const: per4

      - const: per5



  interrupts:

    maxItems: 6



  power-domains:

    maxItems: 6



  ports:

    $ref: /schemas/graph.yaml#/properties/ports

    properties:

      port@2:

        $ref: /schemas/graph.yaml#/properties/port

        description: MIPI CSI-2 RX 0

      port@6:

        $ref: /schemas/graph.yaml#/properties/port

        description: CSI-2 Parallel RX



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts

  - power-domains

  - ports



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/imx8-clock.h>

    #include <dt-bindings/clock/imx8-lpcg.h>

    #include <dt-bindings/firmware/imx/rsrc.h>



    image-controller@58100000 {

        compatible = "fsl,imx8qxp-isi";

        reg = <0x58100000 0x60000>;

        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,

                 <&pdma1_lpcg IMX_LPCG_CLK_0>,

                 <&pdma2_lpcg IMX_LPCG_CLK_0>,

                 <&pdma3_lpcg IMX_LPCG_CLK_0>,

                 <&pdma4_lpcg IMX_LPCG_CLK_0>,

                 <&pdma5_lpcg IMX_LPCG_CLK_0>;

        clock-names = "per0", "per1", "per2", "per3", "per4", "per5";

        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,

                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,

                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@2 {

                reg = <2>;

                endpoint {

                    remote-endpoint = <&mipi_csi0_out>;

                };

            };

        };

    };

...