Commit 0d363282 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Chen-Yu Tsai
Browse files

clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers 



Add the clock drivers for the entire clock tree of MediaTek Helio X10
MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen)
and multimedia clocks (mmsys, mfg, vdecsys, vencsys).

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: default avatarMiles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220921091455.41327-9-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
parent b7520e2d

drivers/clk/mediatek/Kconfig

+37 −0
Original line number Diff line number Diff line
@@ -259,6 +259,43 @@ config COMMON_CLK_MT6779_AUDSYS 
	help

	  This driver supports Mediatek MT6779 audsys clocks.



config COMMON_CLK_MT6795

	tristate "Clock driver for MediaTek MT6795"

	depends on ARCH_MEDIATEK || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT6795 basic clocks and clocks

	  required for various peripherals found on MediaTek.



config COMMON_CLK_MT6795_MFGCFG

	tristate "Clock driver for MediaTek MT6795 mfgcfg"

	depends on COMMON_CLK_MT6795

	default COMMON_CLK_MT6795

	help

	  This driver supports MediaTek MT6795 mfgcfg clocks.



config COMMON_CLK_MT6795_MMSYS

       tristate "Clock driver for MediaTek MT6795 mmsys"

       depends on COMMON_CLK_MT6795

	default COMMON_CLK_MT6795

       help

         This driver supports MediaTek MT6795 mmsys clocks.



config COMMON_CLK_MT6795_VDECSYS

	tristate "Clock driver for MediaTek MT6795 VDECSYS"

	depends on COMMON_CLK_MT6795

	default COMMON_CLK_MT6795

	help

	  This driver supports MediaTek MT6795 vdecsys clocks.



config COMMON_CLK_MT6795_VENCSYS

	tristate "Clock driver for MediaTek MT6795 VENCSYS"

	depends on COMMON_CLK_MT6795

	default COMMON_CLK_MT6795

	help

	  This driver supports MediaTek MT6795 vencsys clocks.



config COMMON_CLK_MT6797

	bool "Clock driver for MediaTek MT6797"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

drivers/clk/mediatek/Makefile

+6 −0
Original line number Diff line number Diff line
@@ -17,6 +17,12 @@ obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o 
obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o

obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o

obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o

obj-$(CONFIG_COMMON_CLK_MT6795) += clk-mt6795-apmixedsys.o clk-mt6795-infracfg.o \

				   clk-mt6795-pericfg.o clk-mt6795-topckgen.o

obj-$(CONFIG_COMMON_CLK_MT6795_MFGCFG) += clk-mt6795-mfg.o

obj-$(CONFIG_COMMON_CLK_MT6795_MMSYS) += clk-mt6795-mm.o

obj-$(CONFIG_COMMON_CLK_MT6795_VDECSYS) += clk-mt6795-vdecsys.o

obj-$(CONFIG_COMMON_CLK_MT6795_VENCSYS) += clk-mt6795-vencsys.o

obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o

obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o

obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o

drivers/clk/mediatek/clk-mt6795-apmixedsys.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 Collabora Ltd.

 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

 */



#include <dt-bindings/clock/mediatek,mt6795-clk.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include "clk-mtk.h"

#include "clk-pll.h"



#define REG_REF2USB		0x8

#define REG_AP_PLL_CON7		0x1c

 #define MD1_MTCMOS_OFF		BIT(0)

 #define MD1_MEM_OFF		BIT(1)

 #define MD1_CLK_OFF		BIT(4)

 #define MD1_ISO_OFF		BIT(8)



#define MT6795_PLL_FMAX		(3000UL * MHZ)

#define MT6795_CON0_EN		BIT(0)

#define MT6795_CON0_RST_BAR	BIT(24)



#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\

	    _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) {	\

		.id = _id,						\

		.name = _name,						\

		.reg = _reg,						\

		.pwr_reg = _pwr_reg,					\

		.en_mask = MT6795_CON0_EN | _en_mask,			\

		.flags = _flags,					\

		.rst_bar_mask = MT6795_CON0_RST_BAR,			\

		.fmax = MT6795_PLL_FMAX,				\

		.pcwbits = _pcwbits,					\

		.pd_reg = _pd_reg,					\

		.pd_shift = _pd_shift,					\

		.tuner_reg = _tuner_reg,				\

		.pcw_reg = _pcw_reg,					\

		.pcw_shift = _pcw_shift,				\

		.div_table = NULL,					\

		.pll_en_bit = 0,					\

	}



static const struct mtk_pll_data plls[] = {

	PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,

	    21, 0x204, 24, 0x0, 0x204, 0),

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,

	    21, 0x220, 4, 0x0, 0x224, 0),

	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,

	    7, 0x230, 4, 0x0, 0x234, 14),

	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),

	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),

	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),

	PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),

	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),

	PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),

	PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),

};



static void clk_mt6795_apmixed_setup_md1(void __iomem *base)

{

	void __iomem *reg = base + REG_AP_PLL_CON7;



	/* Turn on MD1 internal clock */

	writel(readl(reg) & ~MD1_CLK_OFF, reg);



	/* Unlock MD1's MTCMOS power path */

	writel(readl(reg) & ~MD1_MTCMOS_OFF, reg);



	/* Turn on ISO */

	writel(readl(reg) & ~MD1_ISO_OFF, reg);



	/* Turn on memory */

	writel(readl(reg) & ~MD1_MEM_OFF, reg);

}



static const struct of_device_id of_match_clk_mt6795_apmixed[] = {

	{ .compatible = "mediatek,mt6795-apmixedsys" },

	{ /* sentinel */ }

};



static int clk_mt6795_apmixed_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	struct device *dev = &pdev->dev;

	struct device_node *node = dev->of_node;

	void __iomem *base;

	struct clk_hw *hw;

	int ret;



	base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(base))

		return PTR_ERR(base);



	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);

	if (!clk_data)

		return -ENOMEM;



	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);

	if (ret)

		goto free_clk_data;



	hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REG_REF2USB);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		dev_err(dev, "Failed to register ref2usb_tx: %d\n", ret);

		goto unregister_plls;

	}

	clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;



	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (ret) {

		dev_err(dev, "Cannot register clock provider: %d\n", ret);

		goto unregister_ref2usb;

	}



	/* Setup MD1 to avoid random crashes */

	dev_dbg(dev, "Performing initial setup for MD1\n");

	clk_mt6795_apmixed_setup_md1(base);



	return 0;



unregister_ref2usb:

	mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);

unregister_plls:

	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);

free_clk_data:

	mtk_free_clk_data(clk_data);

	return ret;

}



static int clk_mt6795_apmixed_remove(struct platform_device *pdev)

{

	struct device_node *node = pdev->dev.of_node;

	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);



	of_clk_del_provider(node);

	mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);

	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);

	mtk_free_clk_data(clk_data);



	return 0;

}



static struct platform_driver clk_mt6795_apmixed_drv = {

	.probe = clk_mt6795_apmixed_probe,

	.remove = clk_mt6795_apmixed_remove,

	.driver = {

		.name = "clk-mt6795-apmixed",

		.of_match_table = of_match_clk_mt6795_apmixed,

	},

};

module_platform_driver(clk_mt6795_apmixed_drv);



MODULE_DESCRIPTION("MediaTek MT6795 apmixed clocks driver");

MODULE_LICENSE("GPL");

drivers/clk/mediatek/clk-mt6795-infracfg.c

0 → 100644
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Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 Collabora Ltd.

 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

 */



#include <dt-bindings/clock/mediatek,mt6795-clk.h>

#include <dt-bindings/reset/mediatek,mt6795-resets.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include "clk-cpumux.h"

#include "clk-gate.h"

#include "clk-mtk.h"

#include "reset.h"



#define GATE_ICG(_id, _name, _parent, _shift)			\

		GATE_MTK(_id, _name, _parent, &infra_cg_regs,	\

			 _shift, &mtk_clk_gate_ops_no_setclr)



static const struct mtk_gate_regs infra_cg_regs = {

	.set_ofs = 0x0040,

	.clr_ofs = 0x0044,

	.sta_ofs = 0x0048,

};



static const char * const ca53_c0_parents[] = {

	"clk26m",

	"armca53pll",

	"mainpll",

	"univpll"

};



static const char * const ca53_c1_parents[] = {

	"clk26m",

	"armca53pll",

	"mainpll",

	"univpll"

};



static const struct mtk_composite cpu_muxes[] = {

	MUX(CLK_INFRA_CA53_C0_SEL, "infra_ca53_c0_sel", ca53_c0_parents, 0x00, 0, 2),

	MUX(CLK_INFRA_CA53_C1_SEL, "infra_ca53_c1_sel", ca53_c1_parents, 0x00, 2, 2),

};



static const struct mtk_gate infra_gates[] = {

	GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),

	GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),

	GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),

	GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),

	GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),

	GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),

	GATE_ICG(CLK_INFRA_MD1MCU, "infra_md1mcu", "clk26m", 9),

	GATE_ICG(CLK_INFRA_MD1BUS, "infra_md1bus", "axi_sel", 10),

	GATE_ICG(CLK_INFRA_MD1DBB, "infra_dbb", "axi_sel", 11),

	GATE_ICG(CLK_INFRA_DEVICE_APC, "infra_devapc", "clk26m", 12),

	GATE_ICG(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 13),

	GATE_ICG(CLK_INFRA_MD1LTE, "infra_md1lte", "axi_sel", 14),

	GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),

	GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),

};



static u16 infra_ao_rst_ofs[] = { 0x30, 0x34 };



static u16 infra_ao_idx_map[] = {

	[MT6795_INFRA_RST0_SCPSYS_RST]    = 0 * RST_NR_PER_BANK + 5,

	[MT6795_INFRA_RST0_PMIC_WRAP_RST] = 0 * RST_NR_PER_BANK + 7,

	[MT6795_INFRA_RST1_MIPI_DSI_RST]  = 1 * RST_NR_PER_BANK + 4,

	[MT6795_INFRA_RST1_MIPI_CSI_RST]  = 1 * RST_NR_PER_BANK + 7,

	[MT6795_INFRA_RST1_MM_IOMMU_RST]  = 1 * RST_NR_PER_BANK + 15,

};



static const struct mtk_clk_rst_desc clk_rst_desc = {

	.version = MTK_RST_SET_CLR,

	.rst_bank_ofs = infra_ao_rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),

	.rst_idx_map = infra_ao_idx_map,

	.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),

};



static const struct of_device_id of_match_clk_mt6795_infracfg[] = {

	{ .compatible = "mediatek,mt6795-infracfg" },

	{ /* sentinel */ }

};



static int clk_mt6795_infracfg_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	struct device_node *node = pdev->dev.of_node;

	void __iomem *base;

	int ret;



	base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(base))

		return PTR_ERR(base);



	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);

	if (!clk_data)

		return -ENOMEM;



	ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);

	if (ret)

		goto free_clk_data;



	ret = mtk_clk_register_gates(node, infra_gates, ARRAY_SIZE(infra_gates), clk_data);

	if (ret)

		goto free_clk_data;



	ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);

	if (ret)

		goto unregister_gates;



	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (ret)

		goto unregister_cpumuxes;



	return 0;



unregister_cpumuxes:

	mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);

unregister_gates:

	mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);

free_clk_data:

	mtk_free_clk_data(clk_data);

	return ret;

}



static int clk_mt6795_infracfg_remove(struct platform_device *pdev)

{

	struct device_node *node = pdev->dev.of_node;

	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);



	of_clk_del_provider(node);

	mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);

	mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);

	mtk_free_clk_data(clk_data);



	return 0;

}



static struct platform_driver clk_mt6795_infracfg_drv = {

	.driver = {

		.name = "clk-mt6795-infracfg",

		.of_match_table = of_match_clk_mt6795_infracfg,

	},

	.probe = clk_mt6795_infracfg_probe,

	.remove = clk_mt6795_infracfg_remove,

};

module_platform_driver(clk_mt6795_infracfg_drv);



MODULE_DESCRIPTION("MediaTek MT6795 infracfg clocks driver");

MODULE_LICENSE("GPL");

drivers/clk/mediatek/clk-mt6795-mfg.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 Collabora Ltd.

 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

 */



#include <dt-bindings/clock/mediatek,mt6795-clk.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include "clk-gate.h"

#include "clk-mtk.h"



static const struct mtk_gate_regs mfg_cg_regs = {

	.set_ofs = 0x4,

	.clr_ofs = 0x8,

	.sta_ofs = 0x0,

};



#define GATE_MFG(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)



static const struct mtk_gate mfg_clks[] = {

	GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "axi_mfg_in_sel", 0),

	GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "mem_mfg_in_sel", 1),

	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 2),

	GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m", 3),

};



static const struct mtk_clk_desc mfg_desc = {

	.clks = mfg_clks,

	.num_clks = ARRAY_SIZE(mfg_clks),

};



static const struct of_device_id of_match_clk_mt6795_mfg[] = {

	{ .compatible = "mediatek,mt6795-mfgcfg", .data = &mfg_desc },

	{ /* sentinel */ }

};



static struct platform_driver clk_mt6795_mfg_drv = {

	.driver = {

		.name = "clk-mt6795-mfg",

		.of_match_table = of_match_clk_mt6795_mfg,

	},

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

};

module_platform_driver(clk_mt6795_mfg_drv);



MODULE_DESCRIPTION("MediaTek MT6795 mfg clocks driver");

MODULE_LICENSE("GPL");