Commit 0dc85386 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-xe-next-2025-01-10' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next 



Driver Changes:
- SRIOV VF: Avoid reading inaccessible registers (Jakub, Marcin)
 - Introduce RPa frequency information (Rodrigo)
 - Remove unnecessary force wakes on SLPC code (Vinay)
 - Fix all typos in xe (Nitin)
 - Adding steering info support for GuC register lists (Jesus)
 - Remove unused xe_pciids.h harder, add missing PCI ID (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Z4E0tlTAA6MZ7PF2@intel.com
parents 255e094a 6a04bb5a

drivers/gpu/drm/xe/Kconfig.debug

+2 −2
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ config DRM_XE_DEBUG_MEM 
	bool "Enable passing SYS/VRAM addresses to user space"

	default n

	help

	  Pass object location trough uapi. Intended for extended

	  Pass object location through uapi. Intended for extended

	  testing and development only.



	  Recommended for driver developers only.
@@ -104,5 +104,5 @@ config DRM_XE_USERPTR_INVAL_INJECT 
         Choose this option when debugging error paths that

	 are hit during checks for userptr invalidations.



	 Recomended for driver developers only.

	 Recommended for driver developers only.

	 If in doubt, say "N".

drivers/gpu/drm/xe/abi/guc_capture_abi.h

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ enum guc_state_capture_type { 


#define GUC_STATE_CAPTURE_TYPE_MAX	(GUC_STATE_CAPTURE_TYPE_ENGINE_INSTANCE + 1)



/* Class indecies for capture_class and capture_instance arrays */

/* Class indices for capture_class and capture_instance arrays */

enum guc_capture_list_class_type {

	GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0,

	GUC_CAPTURE_LIST_CLASS_VIDEO = 1,

drivers/gpu/drm/xe/abi/guc_klvs_abi.h

+3 −3
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ enum { 
 * _`GUC_KLV_VGT_POLICY_SCHED_IF_IDLE` : 0x8001

 *      This config sets whether strict scheduling is enabled whereby any VF

 *      that doesn’t have work to submit is still allocated a fixed execution

 *      time-slice to ensure active VFs execution is always consitent even

 *      time-slice to ensure active VFs execution is always consistent even

 *      during other VF reprovisiong / rebooting events. Changing this KLV

 *      impacts all VFs and takes effect on the next VF-Switch event.

 *
@@ -207,7 +207,7 @@ enum { 
 *      of and this will never be perfectly-exact (accumulated nano-second

 *      granularity) since the GPUs clock time runs off a different crystal

 *      from the CPUs clock. Changing this KLV on a VF that is currently

 *      running a context wont take effect until a new context is scheduled in.

 *      running a context won't take effect until a new context is scheduled in.

 *      That said, when the PF is changing this value from 0x0 to

 *      a non-zero value, it might never take effect if the VF is running an

 *      infinitely long compute or shader kernel. In such a scenario, the
@@ -227,7 +227,7 @@ enum { 
 *      HW is capable and this will never be perfectly-exact (accumulated

 *      nano-second granularity) since the GPUs clock time runs off a

 *      different crystal from the CPUs clock. Changing this KLV on a VF

 *      that is currently running a context wont take effect until a new

 *      that is currently running a context won't take effect until a new

 *      context is scheduled in.

 *      That said, when the PF is changing this value from 0x0 to

 *      a non-zero value, it might never take effect if the VF is running an

drivers/gpu/drm/xe/regs/xe_reg_defs.h

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
/**

 * struct xe_reg - Register definition

 *

 * Register defintion to be used by the individual register. Although the same

 * Register definition to be used by the individual register. Although the same

 * definition is used for xe_reg and xe_reg_mcr, they use different internal

 * APIs for accesses.

 */

drivers/gpu/drm/xe/regs/xe_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -44,12 +44,16 @@ 


#define MTL_RP_STATE_CAP			XE_REG(0x138000)



#define MTL_GT_RPA_FREQUENCY			XE_REG(0x138008)

#define MTL_GT_RPE_FREQUENCY			XE_REG(0x13800c)



#define MTL_MEDIAP_STATE_CAP			XE_REG(0x138020)

#define   MTL_RPN_CAP_MASK			REG_GENMASK(24, 16)

#define   MTL_RP0_CAP_MASK			REG_GENMASK(8, 0)



#define MTL_MPA_FREQUENCY			XE_REG(0x138028)

#define   MTL_RPA_MASK				REG_GENMASK(8, 0)



#define MTL_MPE_FREQUENCY			XE_REG(0x13802c)

#define   MTL_RPE_MASK				REG_GENMASK(8, 0)