Commit 0de09025 authored by Phil Elwell's avatar Phil Elwell Committed by Florian Fainelli
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ARM: dts: bcm2711: PL011 UARTs are actually r1p5 



The ARM PL011 UART instances in BCM2711 are r1p5 spec, which means they
have 32-entry FIFOs. The correct periphid value for this is 0x00341011.
Thanks to N Buchwitz for pointing this out.

Signed-off-by: default avatarPhil Elwell <phil@raspberrypi.com>
Signed-off-by: default avatarStefan Wahren <wahrenst@gmx.net>
Link: https://lore.kernel.org/r/20250223125614.3592-2-wahrenst@gmx.net


Fixes: 7dbe8c62 ("ARM: dts: Add minimal Raspberry Pi 4 support")
Signed-off-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
parent f44fa354

arch/arm/boot/dts/broadcom/bcm2711.dtsi

+5 −4
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ uart2: serial@7e201400 { 
			clocks = <&clocks BCM2835_CLOCK_UART>,

				 <&clocks BCM2835_CLOCK_VPU>;

			clock-names = "uartclk", "apb_pclk";

			arm,primecell-periphid = <0x00241011>;

			arm,primecell-periphid = <0x00341011>;

			status = "disabled";

		};
@@ -145,7 +145,7 @@ uart3: serial@7e201600 { 
			clocks = <&clocks BCM2835_CLOCK_UART>,

				 <&clocks BCM2835_CLOCK_VPU>;

			clock-names = "uartclk", "apb_pclk";

			arm,primecell-periphid = <0x00241011>;

			arm,primecell-periphid = <0x00341011>;

			status = "disabled";

		};
@@ -156,7 +156,7 @@ uart4: serial@7e201800 { 
			clocks = <&clocks BCM2835_CLOCK_UART>,

				 <&clocks BCM2835_CLOCK_VPU>;

			clock-names = "uartclk", "apb_pclk";

			arm,primecell-periphid = <0x00241011>;

			arm,primecell-periphid = <0x00341011>;

			status = "disabled";

		};
@@ -167,7 +167,7 @@ uart5: serial@7e201a00 { 
			clocks = <&clocks BCM2835_CLOCK_UART>,

				 <&clocks BCM2835_CLOCK_VPU>;

			clock-names = "uartclk", "apb_pclk";

			arm,primecell-periphid = <0x00241011>;

			arm,primecell-periphid = <0x00341011>;

			status = "disabled";

		};
@@ -1178,6 +1178,7 @@ &txp { 
};



&uart0 {

	arm,primecell-periphid = <0x00341011>;

	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

};