Commit 0dea4e30 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.7' of... 

Merge tag 'qcom-clk-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Initial support for the SM4450 Global Clock Controller and RPMh clock controllers
 - Drop CLK_SET_RATE_PARENT for clocks with fixed-rate GPLLs across a variety of IPQ platforms
 - Add missing parent of APCS PLL on IPQ6018
 - Add I2C QUP6 clk on IPQ6018 but mark it critical to avoid problems with RPM
 - Implement safe source switching for a53pll and use on IPQ5332
 - Add support for Stromer Plus PLLs
 - Switch SM8550 Video and GPU clock controllers to use OLE PLL configure method
 - Non critical fixes to halt bit checks
 - Add SMMU GDSC for MSM8998
 - Fix possible integer overflow in RCG frequency calculation code
 - Remove RPM managed clks from MSM8996 GCC driver
 - Add Camera Clock Controller on SM8550
 - Add HFPLL configuration for the three HFPLLs in MSM8976
 - Switch MSM8996 CBF clock driver's remove function to return void

* tag 'qcom-clk-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (36 commits)
  clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
  clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
  clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
  clk: qcom: gcc-ipq6018: add QUP6 I2C clock
  clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
  clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
  clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
  clk: qcom: clk-alpha-pll: introduce stromer plus ops
  clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
  clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure
  clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure
  clk: qcom: Replace of_device.h with explicit includes
  clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect
  clk: qcom: cbf-msm8996: Convert to platform remove callback returning void
  clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src
  clk: qcom: Add GCC driver support for SM4450
  dt-bindings: clock: qcom: Add GCC clocks for SM4450
  ...
parents 0bb80ecc e0e6373d

Documentation/devicetree/bindings/clock/qcom,hfpll.txt

+3 −0
Original line number Diff line number Diff line
@@ -12,6 +12,9 @@ PROPERTIES 
                        "qcom,hfpll-apq8064", "qcom,hfpll"

                        "qcom,hfpll-msm8974", "qcom,hfpll"

                        "qcom,hfpll-msm8960", "qcom,hfpll"

                        "qcom,msm8976-hfpll-a53", "qcom,hfpll"

                        "qcom,msm8976-hfpll-a72", "qcom,hfpll"

                        "qcom,msm8976-hfpll-cci", "qcom,hfpll"



- reg:

	Usage: required

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ properties: 
      - qcom,sdx55-rpmh-clk

      - qcom,sdx65-rpmh-clk

      - qcom,sdx75-rpmh-clk

      - qcom,sm4450-rpmh-clk

      - qcom,sm6350-rpmh-clk

      - qcom,sm8150-rpmh-clk

      - qcom,sm8250-rpmh-clk

Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml

0 → 100644
+55 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on SM4450



maintainers:

  - Ajit Pandey <quic_ajipan@quicinc.com>

  - Taniya Das <quic_tdas@quicinc.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on SM4450



  See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h



properties:

  compatible:

    const: qcom,sm4450-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: UFS Phy Rx symbol 0 clock source

      - description: UFS Phy Rx symbol 1 clock source

      - description: UFS Phy Tx symbol 0 clock source

      - description: USB3 Phy wrapper pipe clock source



required:

  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,sm4450-gcc";

      reg = <0x00100000 0x001f4200>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,

               <&ufs_mem_phy 0>, <&ufs_mem_phy 1>,

               <&ufs_mem_phy 2>, <&usb_1_qmpphy>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

+6 −2
Original line number Diff line number Diff line
@@ -13,11 +13,15 @@ description: | 
  Qualcomm camera clock control module provides the clocks, resets and power

  domains on SM8450.



  See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h

  See also::

    include/dt-bindings/clock/qcom,sm8450-camcc.h

    include/dt-bindings/clock/qcom,sm8550-camcc.h



properties:

  compatible:

    const: qcom,sm8450-camcc

    enum:

      - qcom,sm8450-camcc

      - qcom,sm8550-camcc



  clocks:

    items:

drivers/clk/qcom/Kconfig

+17 −0
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ config IPQ_APSS_6018 
	tristate "IPQ APSS Clock Controller"

	select IPQ_APSS_PLL

	depends on QCOM_APCS_IPC || COMPILE_TEST

	depends on QCOM_SMEM

	help

	  Support for APSS clock controller on IPQ platforms. The

	  APSS clock controller manages the Mux and enable block that feeds the
@@ -764,6 +765,13 @@ config SM_CAMCC_8450 
	  Support for the camera clock controller on SM8450 devices.

	  Say Y if you want to support camera devices and camera functionality.



config SM_CAMCC_8550

	tristate "SM8550 Camera Clock Controller"

	select SM_GCC_8550

	help

	  Support for the camera clock controller on SM8550 devices.

	  Say Y if you want to support camera devices and camera functionality.



config SM_DISPCC_6115

	tristate "SM6115 Display Clock Controller"

	depends on ARM64 || COMPILE_TEST
@@ -834,6 +842,15 @@ config SM_DISPCC_8550 
	  Say Y if you want to support display devices and functionality such as

	  splash screen.



config SM_GCC_4450

	tristate "SM4450 Global Clock Controller"

	depends on ARM64 || COMPILE_TEST

	select QCOM_GDSC

	help

	  Support for the global clock controller on SM4450 devices.

	  Say Y if you want to use peripheral devices such as UART, SPI,

	  I2C, USB, SD/UFS, PCIe, etc.



config SM_GCC_6115

	tristate "SM6115 and SM4250 Global Clock Controller"

	depends on ARM64 || COMPILE_TEST