Commit 0e67f514 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm: merge dpu_format and mdp_format in struct msm_format 



Structures dpu_format and mdp_format are largely the same structures.
In order to remove duplication between format databases, merge these two
stucture definitions into the global struct msm_format.

Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/590434/
Link: https://lore.kernel.org/r/20240420-dpu-format-v2-5-9e93226cbffd@linaro.org
parent 7120d8a0

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

+6 −6
Original line number Diff line number Diff line
@@ -320,7 +320,7 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, 
}



static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,

		struct dpu_plane_state *pstate, struct dpu_format *format)

		struct dpu_plane_state *pstate, const struct msm_format *format)

{

	struct dpu_hw_mixer *lm = mixer->hw_lm;

	uint32_t blend_op;
@@ -363,7 +363,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 
				fg_alpha, bg_alpha, blend_op);



	DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",

		  &format->base.pixel_format, format->alpha_enable, blend_op);

		  &format->pixel_format, format->alpha_enable, blend_op);

}



static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -395,7 +395,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, 
				       struct dpu_crtc_mixer *mixer,

				       u32 num_mixers,

				       enum dpu_stage stage,

				       struct dpu_format *format,

				       const struct msm_format *format,

				       uint64_t modifier,

				       struct dpu_sw_pipe *pipe,

				       unsigned int stage_idx,
@@ -412,7 +412,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, 


	trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),

				   state, to_dpu_plane_state(state), stage_idx,

				   format->base.pixel_format,

				   format->pixel_format,

				   modifier);



	DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
@@ -440,7 +440,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 
	struct drm_plane_state *state;

	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);

	struct dpu_plane_state *pstate = NULL;

	struct dpu_format *format;

	const struct msm_format *format;

	struct dpu_hw_ctl *ctl = mixer->lm_ctl;



	uint32_t lm_idx;
@@ -459,7 +459,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 
		pstate = to_dpu_plane_state(state);

		fb = state->fb;



		format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));

		format = msm_framebuffer_format(pstate->base.fb);



		if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)

			bg_alpha_enable = true;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+6 −6
Original line number Diff line number Diff line
@@ -675,7 +675,7 @@ static int dpu_encoder_virt_atomic_check( 
	if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {

		fb = conn_state->writeback_job->fb;



		if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb))))

		if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))

			topology.needs_cdm = true;

	} else if (disp_info->intf_type == INTF_DP) {

		if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode))
@@ -2184,7 +2184,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 
}



void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,

				       const struct dpu_format *dpu_fmt,

				       const struct msm_format *dpu_fmt,

				       u32 output_type)

{

	struct dpu_hw_cdm *hw_cdm;
@@ -2202,9 +2202,9 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 
	if (!hw_cdm)

		return;



	if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {

	if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {

		DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),

			  &dpu_fmt->base.pixel_format);

			  &dpu_fmt->pixel_format);

		if (hw_cdm->ops.bind_pingpong_blk)

			hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
@@ -2217,7 +2217,7 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 
	cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;

	cdm_cfg->output_fmt = dpu_fmt;

	cdm_cfg->output_type = output_type;

	cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?

	cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?

			CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;

	cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
@@ -2246,7 +2246,7 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 


	DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",

		  DRMID(phys_enc->parent), cdm_cfg->output_width,

		  cdm_cfg->output_height, &cdm_cfg->output_fmt->base.pixel_format,

		  cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,

		  cdm_cfg->output_type, cdm_cfg->output_bit_depth,

		  cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

+1 −1
Original line number Diff line number Diff line
@@ -393,7 +393,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc); 
 * @output_type: HDMI/WB

 */

void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,

				       const struct dpu_format *dpu_fmt,

				       const struct msm_format *dpu_fmt,

				       u32 output_type);



/**

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

+2 −2
Original line number Diff line number Diff line
@@ -235,7 +235,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( 
{

	struct drm_display_mode mode;

	struct dpu_hw_intf_timing_params timing_params = { 0 };

	const struct dpu_format *fmt = NULL;

	const struct msm_format *fmt = NULL;

	u32 fmt_fourcc;

	unsigned long lock_flags;

	struct dpu_hw_intf_cfg intf_cfg = { 0 };
@@ -409,7 +409,7 @@ static int dpu_encoder_phys_vid_control_vblank_irq( 
static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)

{

	struct dpu_hw_ctl *ctl;

	const struct dpu_format *fmt;

	const struct msm_format *fmt;

	u32 fmt_fourcc;



	ctl = phys_enc->hw_ctl;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

+2 −2
Original line number Diff line number Diff line
@@ -322,7 +322,7 @@ static void dpu_encoder_phys_wb_setup( 
	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);

	struct drm_writeback_job *wb_job;

	const struct msm_format *format;

	const struct dpu_format *dpu_fmt;

	const struct msm_format *dpu_fmt;



	wb_job = wb_enc->wb_job;

	format = msm_framebuffer_format(wb_enc->wb_job->fb);
@@ -594,7 +594,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc 
	wb_cfg->dest.height = job->fb->height;

	wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;



	if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&

	if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) &&

			(wb_cfg->dest.format->element[0] == C1_B_Cb))

		swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);