Commit 0e9f4375 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Martin K. Petersen
Browse files

scsi: ufs: qcom: Use ufshcd_rmwl() where applicable 



Instead of using both ufshcd_readl() and ufshcd_writel() to read/modify/
write a register, let's make use of the existing helper.

Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231208065902.11006-17-manivannan.sadhasivam@linaro.org


Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 104cd58d

drivers/ufs/host/ufs-qcom.c

+4 −8
Original line number Diff line number Diff line
@@ -387,8 +387,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 
 */

static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)

{

	ufshcd_writel(hba,

		ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,

	ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,

		    REG_UFS_CFG2);



	/* Ensure that HW clock gating is enabled before next operations */
@@ -1689,11 +1688,8 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba) 
		platform_msi_domain_free_irqs(hba->dev);

	} else {

		if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&

		    host->hw_ver.step == 0) {

			ufshcd_writel(hba,

				      ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000,

				      REG_UFS_CFG3);

		}

		    host->hw_ver.step == 0)

			ufshcd_rmwl(hba, ESI_VEC_MASK, 0x1f00, REG_UFS_CFG3);

		ufshcd_mcq_enable_esi(hba);

	}

drivers/ufs/host/ufs-qcom.h

+3 −0
Original line number Diff line number Diff line
@@ -102,6 +102,9 @@ enum { 
#define TMRLUT_HW_CGC_EN	BIT(6)

#define OCSC_HW_CGC_EN		BIT(7)



/* bit definitions for REG_UFS_CFG3 register */

#define ESI_VEC_MASK		GENMASK(22, 12)



/* bit definitions for REG_UFS_PARAM0 */

#define MAX_HS_GEAR_MASK	GENMASK(6, 4)

#define UFS_QCOM_MAX_GEAR(x)	FIELD_GET(MAX_HS_GEAR_MASK, (x))