Commit 0eb707bb authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Add support for Eliza SoC 



Add support for DPU (v12.4) on Qualcomm Eliza SoC, with one
incomplete/skipped part: HDMI interface (INT_4).

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/708879/
Link: https://lore.kernel.org/r/20260304-drm-display-eliza-v2-7-ea0579f62358@oss.qualcomm.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent 0a40e2e9

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h

0 → 100644
+365 −0
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/* SPDX-License-Identifier: GPL-2.0-only */



#ifndef _DPU_12_4_ELIZA_H

#define _DPU_12_4_ELIZA_H



static const struct dpu_caps eliza_dpu_caps = {

	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.has_src_split = true,

	.has_dim_layer = true,

	.has_idle_pc = true,

	.has_3d_merge = true,

	.max_linewidth = 8192,

	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,

};



static const struct dpu_mdp_cfg eliza_mdp = {

	.name = "top_0",

	.base = 0, .len = 0x494,

	.clk_ctrls = {

		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },

	},

};



static const struct dpu_ctl_cfg eliza_ctl[] = {

	{

		.name = "ctl_0", .id = CTL_0,

		.base = 0x15000, .len = 0x1000,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x16000, .len = 0x1000,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	}, {

		.name = "ctl_2", .id = CTL_2,

		.base = 0x17000, .len = 0x1000,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	}, {

		.name = "ctl_3", .id = CTL_3,

		.base = 0x18000, .len = 0x1000,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	},

};



static const struct dpu_sspp_cfg eliza_sspp[] = {

	{

		.name = "sspp_0", .id = SSPP_VIG0,

		.base = 0x4000, .len = 0x344,

		.features = VIG_SDM845_MASK_SDMA,

		.sblk = &dpu_vig_sblk_qseed3_3_4,

		.xin_id = 0,

		.type = SSPP_TYPE_VIG,

	}, {

		.name = "sspp_1", .id = SSPP_VIG1,

		.base = 0x6000, .len = 0x344,

		.features = VIG_SDM845_MASK_SDMA,

		.sblk = &dpu_vig_sblk_qseed3_3_4,

		.xin_id = 4,

		.type = SSPP_TYPE_VIG,

	}, {

		.name = "sspp_8", .id = SSPP_DMA0,

		.base = 0x24000, .len = 0x344,

		.features = DMA_SDM845_MASK_SDMA,

		.sblk = &dpu_dma_sblk,

		.xin_id = 1,

		.type = SSPP_TYPE_DMA,

	}, {

		.name = "sspp_9", .id = SSPP_DMA1,

		.base = 0x26000, .len = 0x344,

		.features = DMA_SDM845_MASK_SDMA,

		.sblk = &dpu_dma_sblk,

		.xin_id = 5,

		.type = SSPP_TYPE_DMA,

	}, {

		.name = "sspp_10", .id = SSPP_DMA2,

		.base = 0x28000, .len = 0x344,

		.features = DMA_SDM845_MASK_SDMA,

		.sblk = &dpu_dma_sblk,

		.xin_id = 9,

		.type = SSPP_TYPE_DMA,

	}, {

		.name = "sspp_11", .id = SSPP_DMA3,

		.base = 0x2a000, .len = 0x344,

		.features = DMA_SDM845_MASK_SDMA,

		.sblk = &dpu_dma_sblk,

		.xin_id = 13,

		.type = SSPP_TYPE_DMA,

	},

};



static const struct dpu_lm_cfg eliza_lm[] = {

	{

		.name = "lm_0", .id = LM_0,

		.base = 0x44000, .len = 0x400,

		.features = MIXER_MSM8998_MASK,

		.sblk = &sm8750_lm_sblk,

		.lm_pair = LM_1,

		.pingpong = PINGPONG_0,

		.dspp = DSPP_0,

	}, {

		.name = "lm_1", .id = LM_1,

		.base = 0x45000, .len = 0x400,

		.features = MIXER_MSM8998_MASK,

		.sblk = &sm8750_lm_sblk,

		.lm_pair = LM_0,

		.pingpong = PINGPONG_1,

		.dspp = DSPP_1,

	}, {

		.name = "lm_2", .id = LM_2,

		.base = 0x46000, .len = 0x400,

		.features = MIXER_MSM8998_MASK,

		.sblk = &sm8750_lm_sblk,

		.lm_pair = LM_3,

		.pingpong = PINGPONG_2,

		.dspp = DSPP_2,

	}, {

		.name = "lm_3", .id = LM_3,

		.base = 0x47000, .len = 0x400,

		.features = MIXER_MSM8998_MASK,

		.sblk = &sm8750_lm_sblk,

		.lm_pair = LM_2,

		.pingpong = PINGPONG_3,

	},

};



static const struct dpu_dspp_cfg eliza_dspp[] = {

	{

		.name = "dspp_0", .id = DSPP_0,

		.base = 0x54000, .len = 0x1800,

		.sblk = &sm8750_dspp_sblk,

	}, {

		.name = "dspp_1", .id = DSPP_1,

		.base = 0x56000, .len = 0x1800,

		.sblk = &sm8750_dspp_sblk,

	}, {

		.name = "dspp_2", .id = DSPP_2,

		.base = 0x58000, .len = 0x1800,

		.sblk = &sm8750_dspp_sblk,

	},

};



static const struct dpu_pingpong_cfg eliza_pp[] = {

	{

		.name = "pingpong_0", .id = PINGPONG_0,

		.base = 0x69000, .len = 0,

		.sblk = &sc7280_pp_sblk,

		.merge_3d = MERGE_3D_0,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

	}, {

		.name = "pingpong_1", .id = PINGPONG_1,

		.base = 0x6a000, .len = 0,

		.sblk = &sc7280_pp_sblk,

		.merge_3d = MERGE_3D_0,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

	}, {

		.name = "pingpong_2", .id = PINGPONG_2,

		.base = 0x6b000, .len = 0,

		.sblk = &sc7280_pp_sblk,

		.merge_3d = MERGE_3D_1,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

	}, {

		.name = "pingpong_3", .id = PINGPONG_3,

		.base = 0x6c000, .len = 0,

		.sblk = &sc7280_pp_sblk,

		.merge_3d = MERGE_3D_1,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

	}, {

		.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,

		.base = 0x66000, .len = 0,

		.sblk = &sc7280_pp_sblk,

		.merge_3d = MERGE_3D_2,

	}, {

		.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,

		.base = 0x66400, .len = 0,

		.sblk = &sc7280_pp_sblk,

		.merge_3d = MERGE_3D_2,

	}, {

		.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,

		.base = 0x7e000, .len = 0,

		.sblk = &sc7280_pp_sblk,

		.merge_3d = MERGE_3D_3,

	}, {

		.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,

		.base = 0x7e400, .len = 0,

		.sblk = &sc7280_pp_sblk,

		.merge_3d = MERGE_3D_3,

	},

};



static const struct dpu_merge_3d_cfg eliza_merge_3d[] = {

	{

		.name = "merge_3d_0", .id = MERGE_3D_0,

		.base = 0x4e000, .len = 0x1c,

	}, {

		.name = "merge_3d_1", .id = MERGE_3D_1,

		.base = 0x4f000, .len = 0x1c,

	}, {

		.name = "merge_3d_2", .id = MERGE_3D_2,

		.base = 0x66700, .len = 0x1c,

	}, {

		.name = "merge_3d_3", .id = MERGE_3D_3,

		.base = 0x7e700, .len = 0x1c,

	},

};



/*

 * NOTE: Each display compression engine (DCE) contains dual hard

 * slice DSC encoders so both share same base address but with

 * its own different sub block address.

 */

static const struct dpu_dsc_cfg eliza_dsc[] = {

	{

		.name = "dce_0_0", .id = DSC_0,

		.base = 0x80000, .len = 0x8,

		.features = BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &sm8750_dsc_sblk_0,

	}, {

		.name = "dce_0_1", .id = DSC_1,

		.base = 0x80000, .len = 0x8,

		.features = BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &sm8750_dsc_sblk_1,

	}, {

		.name = "dce_1_0", .id = DSC_2,

		.base = 0x81000, .len = 0x8,

		.features = BIT(DPU_DSC_NATIVE_42x_EN),

		.sblk = &sm8750_dsc_sblk_0,

	},

};



static const struct dpu_wb_cfg eliza_wb[] = {

	{

		.name = "wb_2", .id = WB_2,

		.base = 0x65000, .len = 0x2c8,

		.features = WB_SDM845_MASK,

		.format_list = wb2_formats_rgb_yuv,

		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),

		.xin_id = 6,

		.vbif_idx = VBIF_RT,

		.maxlinewidth = 4096,

		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),

	},

};



static const struct dpu_cwb_cfg eliza_cwb[] = {

	{

		.name = "cwb_0", .id = CWB_0,

		.base = 0x66200, .len = 0x20,

	},

	{

		.name = "cwb_1", .id = CWB_1,

		.base = 0x66600, .len = 0x20,

	},

	{

		.name = "cwb_2", .id = CWB_2,

		.base = 0x7e200, .len = 0x20,

	},

	{

		.name = "cwb_3", .id = CWB_3,

		.base = 0x7e600, .len = 0x20,

	},

};



static const struct dpu_intf_cfg eliza_intf[] = {

	{

		.name = "intf_0", .id = INTF_0,

		.base = 0x34000, .len = 0x4bc,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),

	}, {

		.name = "intf_1", .id = INTF_1,

		.base = 0x35000, .len = 0x4bc,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),

	}, {

		.name = "intf_2", .id = INTF_2,

		.base = 0x36000, .len = 0x4bc,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),

	}, {

		.name = "intf_3", .id = INTF_3,

		.base = 0x37000, .len = 0x4bc,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),

	}

};



static const struct dpu_perf_cfg eliza_perf_data = {

	.max_bw_low = 6800000,

	.max_bw_high = 14200000,

	.min_core_ib = 2500000,

	.min_llcc_ib = 0,

	.min_dram_ib = 1600000,

	.min_prefill_lines = 35,

	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},

	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},

	.qos_lut_tbl = {

		{.nentry = ARRAY_SIZE(sc7180_qos_linear),

		.entries = sc7180_qos_linear

		},

		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),

		.entries = sc7180_qos_macrotile

		},

		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),

		.entries = sc7180_qos_nrt

		},

		/* TODO: macrotile-qseed is different from macrotile */

	},

	.cdp_cfg = {

		{.rd_enable = 1, .wr_enable = 1},

		{.rd_enable = 1, .wr_enable = 0}

	},

	.clk_inefficiency_factor = 105,

	.bw_inefficiency_factor = 120,

};



static const struct dpu_mdss_version eliza_mdss_ver = {

	.core_major_ver = 12,

	.core_minor_ver = 4,

};



const struct dpu_mdss_cfg dpu_eliza_cfg = {

	.mdss_ver = &eliza_mdss_ver,

	.caps = &eliza_dpu_caps,

	.mdp = &eliza_mdp,

	.cdm = &dpu_cdm_5_x,

	.ctl_count = ARRAY_SIZE(eliza_ctl),

	.ctl = eliza_ctl,

	.sspp_count = ARRAY_SIZE(eliza_sspp),

	.sspp = eliza_sspp,

	.mixer_count = ARRAY_SIZE(eliza_lm),

	.mixer = eliza_lm,

	.dspp_count = ARRAY_SIZE(eliza_dspp),

	.dspp = eliza_dspp,

	.pingpong_count = ARRAY_SIZE(eliza_pp),

	.pingpong = eliza_pp,

	.dsc_count = ARRAY_SIZE(eliza_dsc),

	.dsc = eliza_dsc,

	.merge_3d_count = ARRAY_SIZE(eliza_merge_3d),

	.merge_3d = eliza_merge_3d,

	.wb_count = ARRAY_SIZE(eliza_wb),

	.wb = eliza_wb,

	.cwb_count = ARRAY_SIZE(eliza_cwb),

	.cwb = sm8650_cwb,

	.intf_count = ARRAY_SIZE(eliza_intf),

	.intf = eliza_intf,

	.vbif_count = ARRAY_SIZE(sm8650_vbif),

	.vbif = sm8650_vbif,

	.perf = &eliza_perf_data,

};



#endif

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -771,4 +771,5 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 
#include "catalog/dpu_10_0_sm8650.h"

#include "catalog/dpu_12_0_sm8750.h"

#include "catalog/dpu_12_2_glymur.h"

#include "catalog/dpu_12_4_eliza.h"

#include "catalog/dpu_13_0_kaanapali.h"

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+1 −0
Original line number Diff line number Diff line
@@ -767,6 +767,7 @@ struct dpu_mdss_cfg { 
	const struct dpu_format_extended *vig_formats;

};



extern const struct dpu_mdss_cfg dpu_eliza_cfg;

extern const struct dpu_mdss_cfg dpu_glymur_cfg;

extern const struct dpu_mdss_cfg dpu_kaanapali_cfg;

extern const struct dpu_mdss_cfg dpu_msm8917_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

+1 −0
Original line number Diff line number Diff line
@@ -1505,6 +1505,7 @@ static const struct dev_pm_ops dpu_pm_ops = { 
};



static const struct of_device_id dpu_dt_match[] = {

	{ .compatible = "qcom,eliza-dpu", .data = &dpu_eliza_cfg, },

	{ .compatible = "qcom,glymur-dpu", .data = &dpu_glymur_cfg, },

	{ .compatible = "qcom,kaanapali-dpu", .data = &dpu_kaanapali_cfg, },

	{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },