Commit 0f4869b1 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/display: convert I915_STATE_WARN() to struct intel_display 



Convert I915_STATE_WARN() to struct intel_display *, and rename to
INTEL_DISPLAY_STATE_WARN(). Do some minor opportunistic struct
drm_i915_private to struct intel_display conversions while at it.

v2: crtc_state may be NULL in intel_connector_verify_state()

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241024162510.2410128-1-jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 8c2659de

drivers/gpu/drm/i915/display/g4x_dp.c

+7 −8
Original line number Diff line number Diff line
@@ -170,10 +170,9 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state) 
{

	struct intel_display *display = to_intel_display(intel_dp);

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;



	I915_STATE_WARN(dev_priv, cur_state != state,

	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

				 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",

				 dig_port->base.base.base.id, dig_port->base.base.name,

				 str_on_off(state), str_on_off(cur_state));
@@ -185,7 +184,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 
	struct intel_display *display = &dev_priv->display;

	bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;



	I915_STATE_WARN(dev_priv, cur_state != state,

	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

				 "eDP PLL state assertion failure (expected %s, current %s)\n",

				 str_on_off(state), str_on_off(cur_state));

}

drivers/gpu/drm/i915/display/intel_crtc.c

+4 −4
Original line number Diff line number Diff line
@@ -36,9 +36,9 @@ 


static void assert_vblank_disabled(struct drm_crtc *crtc)

{

	struct drm_i915_private *i915 = to_i915(crtc->dev);

	struct intel_display *display = to_intel_display(crtc->dev);



	if (I915_STATE_WARN(i915, drm_crtc_vblank_get(crtc) == 0,

	if (INTEL_DISPLAY_STATE_WARN(display, drm_crtc_vblank_get(crtc) == 0,

				     "[CRTC:%d:%s] vblank assertion failure (expected off, current on)\n",

				     crtc->base.id, crtc->name))

		drm_crtc_vblank_put(crtc);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+38 −38
Original line number Diff line number Diff line
@@ -3279,25 +3279,25 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state, 
				      struct intel_encoder *encoder,

				      struct intel_c10pll_state *mpllb_hw_state)

{

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	struct intel_display *display = to_intel_display(state);

	const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10;

	int i;



	for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {

		u8 expected = mpllb_sw_state->pll[i];



		I915_STATE_WARN(i915, mpllb_hw_state->pll[i] != expected,

		INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected,

					 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",

					 crtc->base.base.id, crtc->base.name, i,

					 expected, mpllb_hw_state->pll[i]);

	}



	I915_STATE_WARN(i915, mpllb_hw_state->tx != mpllb_sw_state->tx,

	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx,

				 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)",

				 crtc->base.base.id, crtc->base.name,

				 mpllb_sw_state->tx, mpllb_hw_state->tx);



	I915_STATE_WARN(i915, mpllb_hw_state->cmn != mpllb_sw_state->cmn,

	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn,

				 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)",

				 crtc->base.base.id, crtc->base.name,

				 mpllb_sw_state->cmn, mpllb_hw_state->cmn);
@@ -3386,33 +3386,33 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state, 
				      struct intel_encoder *encoder,

				      struct intel_c20pll_state *mpll_hw_state)

{

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	struct intel_display *display = to_intel_display(state);

	const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;

	bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);

	bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);

	int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);

	int i;



	I915_STATE_WARN(i915, mpll_hw_state->clock != clock,

	INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock,

				 "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",

				 crtc->base.base.id, crtc->base.name,

				 mpll_sw_state->clock, mpll_hw_state->clock);



	I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,

	INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb,

				 "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",

				 crtc->base.base.id, crtc->base.name,

				 sw_use_mpllb, hw_use_mpllb);



	if (hw_use_mpllb) {

		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {

			I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],

			INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],

						 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",

						 crtc->base.base.id, crtc->base.name, i,

						 mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]);

		}

	} else {

		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {

			I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],

			INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],

						 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",

						 crtc->base.base.id, crtc->base.name, i,

						 mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
@@ -3420,14 +3420,14 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state, 
	}



	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {

		I915_STATE_WARN(i915, mpll_hw_state->tx[i] != mpll_sw_state->tx[i],

		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i],

					 "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)",

					 crtc->base.base.id, crtc->base.name, i,

					 mpll_sw_state->tx[i], mpll_hw_state->tx[i]);

	}



	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) {

		I915_STATE_WARN(i915, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],

		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],

					 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)",

					 crtc->base.base.id, crtc->base.name, i,

					 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]);

drivers/gpu/drm/i915/display/intel_display.c

+10 −9
Original line number Diff line number Diff line
@@ -422,6 +422,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 
void assert_transcoder(struct drm_i915_private *dev_priv,

		       enum transcoder cpu_transcoder, bool state)

{

	struct intel_display *display = &dev_priv->display;

	bool cur_state;

	enum intel_display_power_domain power_domain;

	intel_wakeref_t wakeref;
@@ -442,7 +443,7 @@ void assert_transcoder(struct drm_i915_private *dev_priv, 
		cur_state = false;

	}



	I915_STATE_WARN(dev_priv, cur_state != state,

	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

				 "transcoder %s assertion failure (expected %s, current %s)\n",

				 transcoder_name(cpu_transcoder), str_on_off(state),

				 str_on_off(cur_state));
@@ -450,13 +451,13 @@ void assert_transcoder(struct drm_i915_private *dev_priv, 


static void assert_plane(struct intel_plane *plane, bool state)

{

	struct drm_i915_private *i915 = to_i915(plane->base.dev);

	struct intel_display *display = to_intel_display(plane->base.dev);

	enum pipe pipe;

	bool cur_state;



	cur_state = plane->get_hw_state(plane, &pipe);



	I915_STATE_WARN(i915, cur_state != state,

	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

				 "%s assertion failure (expected %s, current %s)\n",

				 plane->base.name, str_on_off(state),

				 str_on_off(cur_state));

drivers/gpu/drm/i915/display/intel_display.h

+8 −9
Original line number Diff line number Diff line
@@ -585,18 +585,17 @@ void assert_transcoder(struct drm_i915_private *dev_priv, 
bool assert_port_valid(struct drm_i915_private *i915, enum port port);



/*

 * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity

 * checks to check for unexpected conditions which may not necessarily be a user

 * visible problem. This will either WARN() or DRM_ERROR() depending on the

 * verbose_state_checks module param, to enable distros and users to tailor

 * their preferred amount of i915 abrt spam.

 * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw

 * state sanity checks to check for unexpected conditions which may not

 * necessarily be a user visible problem. This will either drm_WARN() or

 * drm_err() depending on the verbose_state_checks module param, to enable

 * distros and users to tailor their preferred amount of i915 abrt spam.

 */

#define I915_STATE_WARN(__i915, condition, format...) ({		\

	struct drm_device *drm = &(__i915)->drm;			\

#define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({	\

	int __ret_warn_on = !!(condition);				\

	if (unlikely(__ret_warn_on))					\

		if (!drm_WARN(drm, __i915->display.params.verbose_state_checks, format)) \

			drm_err(drm, format);				\

		if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \

			drm_err((__display)->drm, format);		\

	unlikely(__ret_warn_on);					\

})