Unverified Commit 0f718660 authored by Kai Vehmanen's avatar Kai Vehmanen Committed by Mark Brown
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ASoC: SOF: Intel: hda: modify period size constraints for ACE4 



Intel ACE4 based products set more strict constraints on HDA BDLE start
address and length alignment. Add a constraint to align period size to
128 bytes.

The commit removes the "minimum as per HDA spec" comment. This comment
was misleading as spec actually does allow a 2 byte BDLE length, and
more importantly, period size also directly impacts how the BDLE start
addresses are aligned, so it is not sufficient just to consider allowed
buffer length.

Fixes: d3df422f ("ASoC: SOF: Intel: add initial support for NVL-S")
Cc: stable@vger.kernel.org
Reported-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: default avatarPéter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarLiam Girdwood <liam.r.girdwood@intel.com>
Link: https://patch.msgid.link/20260408084514.24325-3-peter.ujfalusi@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f4c90fb7

sound/soc/sof/intel/hda-pcm.c

+12 −2
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ EXPORT_SYMBOL_NS(hda_dsp_pcm_pointer, "SND_SOC_SOF_INTEL_HDA_COMMON"); 
int hda_dsp_pcm_open(struct snd_sof_dev *sdev,

		     struct snd_pcm_substream *substream)

{

	const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);

	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);

	struct snd_pcm_runtime *runtime = substream->runtime;

	struct snd_soc_component *scomp = sdev->component;
@@ -268,8 +269,17 @@ int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 
		return -ENODEV;

	}



	/* minimum as per HDA spec */

	snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);

	/*

	 * Set period size constraint to ensure BDLE buffer length and

	 * start address alignment requirements are met. Align to 128

	 * bytes for newer Intel platforms, with older ones using 4 byte alignment.

	 */

	if (chip_info->hw_ip_version >= SOF_INTEL_ACE_4_0)

		snd_pcm_hw_constraint_step(substream->runtime, 0,

					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 128);

	else

		snd_pcm_hw_constraint_step(substream->runtime, 0,

					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);



	/* avoid circular buffer wrap in middle of period */

	snd_pcm_hw_constraint_integer(substream->runtime,