Commit 0fe69062 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu/mes: init aggregated doorbell 



Allocate and enable aggregated doorbell.

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f1549c09

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+12 −4
Original line number Diff line number Diff line
@@ -114,8 +114,14 @@ static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev) 
	size_t doorbell_start_offset;

	size_t doorbell_aperture_size;

	size_t doorbell_process_limit;

	size_t aggregated_doorbell_start;

	int i;



	doorbell_start_offset = (adev->doorbell_index.max_assignment+1) * sizeof(u32);

	aggregated_doorbell_start = (adev->doorbell_index.max_assignment + 1) * sizeof(u32);

	aggregated_doorbell_start =

		roundup(aggregated_doorbell_start, PAGE_SIZE);



	doorbell_start_offset = aggregated_doorbell_start + PAGE_SIZE;

	doorbell_start_offset =

		roundup(doorbell_start_offset,

			amdgpu_mes_doorbell_process_slice(adev));
@@ -135,6 +141,11 @@ static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev) 
	adev->mes.doorbell_id_offset = doorbell_start_offset / sizeof(u32);

	adev->mes.max_doorbell_slices = doorbell_process_limit;



	/* allocate Qword range for aggregated doorbell */

	for (i = 0; i < AMDGPU_MES_PRIORITY_NUM_LEVELS; i++)

		adev->mes.aggregated_doorbells[i] =

			aggregated_doorbell_start / sizeof(u32) + i * 2;



	DRM_INFO("max_doorbell_slices=%zu\n", doorbell_process_limit);

	return 0;

}
@@ -174,9 +185,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) 
			adev->mes.sdma_hqd_mask[i] = 0xfc;

	}



	for (i = 0; i < AMDGPU_MES_PRIORITY_NUM_LEVELS; i++)

		adev->mes.agreegated_doorbells[i] = 0xffffffff;



	r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs);

	if (r) {

		dev_err(adev->dev,

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ struct amdgpu_mes { 
	uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];

	uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];

	uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];

	uint32_t                        agreegated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];

	uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];

	uint32_t                        sch_ctx_offs;

	uint64_t			sch_ctx_gpu_addr;

	uint64_t			*sch_ctx_ptr;

drivers/gpu/drm/amd/amdgpu/mes_v10_1.c

+57 −1
Original line number Diff line number Diff line
@@ -294,7 +294,7 @@ static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) 


	for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)

		mes_set_hw_res_pkt.aggregated_doorbells[i] =

			mes->agreegated_doorbells[i];

			mes->aggregated_doorbells[i];



	for (i = 0; i < 5; i++) {

		mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
@@ -313,6 +313,60 @@ static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) 
			offsetof(union MESAPI_SET_HW_RESOURCES, api_status));

}



static void mes_v10_1_init_aggregated_doorbell(struct amdgpu_mes *mes)

{

	struct amdgpu_device *adev = mes->adev;

	uint32_t data;



	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1);

	data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<

		CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1, data);



	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2);

	data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<

		CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2, data);



	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3);

	data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<

		CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3, data);



	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4);

	data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<

		CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4, data);



	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5);

	data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<

		CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5, data);



	data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;

	WREG32_SOC15(GC, 0, mmCP_HQD_GFX_CONTROL, data);

}



static const struct amdgpu_mes_funcs mes_v10_1_funcs = {

	.add_hw_queue = mes_v10_1_add_hw_queue,

	.remove_hw_queue = mes_v10_1_remove_hw_queue,
@@ -1112,6 +1166,8 @@ static int mes_v10_1_hw_init(void *handle) 
	if (r)

		goto failure;



	mes_v10_1_init_aggregated_doorbell(&adev->mes);



	r = mes_v10_1_query_sched_status(&adev->mes);

	if (r) {

		DRM_ERROR("MES is busy\n");