Commit 1046bc7b authored by Matt Roper's avatar Matt Roper
Browse files

drm/xe/xe2_hpg: Drop invalid workaround Wa_15010599737 



Wa_15010599737 was a workaround originally proposed (and ultimately
rejected) for DG2-G10.  There's no record of it ever being relevant or
even considered for any other platforms.

The specific bit this workaround was setting is documented as "This bit
should be set to 1 for the DX9 API and 0 for all other APIs" which means
that it should almost always be left at the default value of 0 on Linux.
The register itself is directly accessible from userspace, so in the
special cases where it might be relevant (e.g., Wine/Proton running
Windows DX9 apps), the userspace drivers already have the ability to
change the setting without involvement of the kernel.

Fixes: 7f3ee7d8 ("drm/xe/xe2hpg: Add initial GT workarounds")
Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patch.msgid.link/20260223-forupstream-wa_cleanup-v3-2-7f201eb2f172@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent ef547cf1

drivers/gpu/drm/xe/xe_wa.c

+1 −4
Original line number Diff line number Diff line
@@ -731,10 +731,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	},



	/* Xe2_HPG */

	{ XE_RTP_NAME("15010599737"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))

	},



	{ XE_RTP_NAME("14020756599"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))