Commit 10f84de2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-fixes-for-6.10' of... 

Merge tag 'qcom-clk-fixes-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes

Pull Qualcomm clk driver fixes from Bjorn Andersson:

 - Correct the Stromer Plus PLL set_rate to explicitly set ALPHA_EN bit and
   remove unnecessary upper parts of CONFIG_CTL values.
 - Mark the recently added IPQ9574 GCC crypto clocks BRANCH_HALT_VOTED, to
   address stuck clock warnings.
 - Fix the GPLL6 and GPLL7 parents on SM6350 to avoid issues with these
   reportedly running at ~25GHz.

* tag 'qcom-clk-fixes-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  clk: qcom: gcc-ipq9574: Add BRANCH_HALT_VOTED flag
  clk: qcom: apss-ipq-pll: remove 'config_ctl_hi_val' from Stromer pll configs
  clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
  clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents
parents 878e845d 72ceafb5

drivers/clk/qcom/apss-ipq-pll.c

+0 −2
Original line number Diff line number Diff line
@@ -70,7 +70,6 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = { 
static const struct alpha_pll_config ipq5018_pll_config = {

	.l = 0x2a,

	.config_ctl_val = 0x4001075b,

	.config_ctl_hi_val = 0x304,

	.main_output_mask = BIT(0),

	.aux_output_mask = BIT(1),

	.early_output_mask = BIT(3),
@@ -84,7 +83,6 @@ static const struct alpha_pll_config ipq5018_pll_config = { 
static const struct alpha_pll_config ipq5332_pll_config = {

	.l = 0x2d,

	.config_ctl_val = 0x4001075b,

	.config_ctl_hi_val = 0x304,

	.main_output_mask = BIT(0),

	.aux_output_mask = BIT(1),

	.early_output_mask = BIT(3),

drivers/clk/qcom/clk-alpha-pll.c

+3 −0
Original line number Diff line number Diff line
@@ -2574,6 +2574,9 @@ static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 
	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),

					a >> ALPHA_BITWIDTH);



	regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),

			   PLL_ALPHA_EN, PLL_ALPHA_EN);



	regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);



	/* Wait five micro seconds or more */

drivers/clk/qcom/gcc-ipq9574.c

+6 −4
Original line number Diff line number Diff line
@@ -2140,9 +2140,10 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 


static struct clk_branch gcc_crypto_axi_clk = {

	.halt_reg = 0x16010,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x16010,

		.enable_mask = BIT(0),

		.enable_reg = 0xb004,

		.enable_mask = BIT(15),

		.hw.init = &(const struct clk_init_data) {

			.name = "gcc_crypto_axi_clk",

			.parent_hws = (const struct clk_hw *[]) {
@@ -2156,9 +2157,10 @@ static struct clk_branch gcc_crypto_axi_clk = { 


static struct clk_branch gcc_crypto_ahb_clk = {

	.halt_reg = 0x16014,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x16014,

		.enable_mask = BIT(0),

		.enable_reg = 0xb004,

		.enable_mask = BIT(16),

		.hw.init = &(const struct clk_init_data) {

			.name = "gcc_crypto_ahb_clk",

			.parent_hws = (const struct clk_hw *[]) {

drivers/clk/qcom/gcc-sm6350.c

+5 −5
Original line number Diff line number Diff line
@@ -100,8 +100,8 @@ static struct clk_alpha_pll gpll6 = { 
		.enable_mask = BIT(6),

		.hw.init = &(struct clk_init_data){

			.name = "gpll6",

			.parent_hws = (const struct clk_hw*[]){

				&gpll0.clkr.hw,

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "bi_tcxo",

			},

			.num_parents = 1,

			.ops = &clk_alpha_pll_fixed_fabia_ops,
@@ -124,7 +124,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_even = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll6_out_even",

		.parent_hws = (const struct clk_hw*[]){

			&gpll0.clkr.hw,

			&gpll6.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_alpha_pll_postdiv_fabia_ops,
@@ -139,8 +139,8 @@ static struct clk_alpha_pll gpll7 = { 
		.enable_mask = BIT(7),

		.hw.init = &(struct clk_init_data){

			.name = "gpll7",

			.parent_hws = (const struct clk_hw*[]){

				&gpll0.clkr.hw,

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "bi_tcxo",

			},

			.num_parents = 1,

			.ops = &clk_alpha_pll_fixed_fabia_ops,