Commit 11016c79 authored by Abhijit Gangurde's avatar Abhijit Gangurde Committed by Leon Romanovsky
Browse files

net: ionic: Provide doorbell and CMB region information 



The RDMA device needs information of controller memory bar and
doorbell capability to share with user context. Discover CMB regions
and express doorbell capabilities on device init.

Reviewed-by: default avatarShannon Nelson <shannon.nelson@amd.com>
Co-developed-by: default avatarPablo Cascón <pablo.cascon@amd.com>
Signed-off-by: default avatarPablo Cascón <pablo.cascon@amd.com>
Co-developed-by: default avatarAllen Hubbe <allen.hubbe@amd.com>
Signed-off-by: default avatarAllen Hubbe <allen.hubbe@amd.com>
Signed-off-by: default avatarAbhijit Gangurde <abhijit.gangurde@amd.com>
Link: https://patch.msgid.link/20250903061606.4139957-7-abhijit.gangurde@amd.com


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 2dc6a6a6

drivers/net/ethernet/pensando/ionic/ionic_api.h

+22 −0
Original line number Diff line number Diff line
@@ -106,4 +106,26 @@ int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr); 
 */

void ionic_intr_free(struct ionic_lif *lif, int intr);



/**

 * ionic_get_cmb - Reserve cmb pages

 * @lif:         Logical interface

 * @pgid:        First page index

 * @pgaddr:      First page bus addr (contiguous)

 * @order:       Log base two number of pages (PAGE_SIZE)

 * @stride_log2: Size of stride to determine CMB pool

 * @expdb:       Will be set to true if this CMB region has expdb enabled

 *

 * Return: zero or negative error status

 */

int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr,

		  int order, u8 stride_log2, bool *expdb);



/**

 * ionic_put_cmb - Release cmb pages

 * @lif:        Logical interface

 * @pgid:       First page index

 * @order:      Log base two number of pages (PAGE_SIZE)

 */

void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order);



#endif /* _IONIC_API_H_ */

drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c

+2 −0
Original line number Diff line number Diff line
@@ -272,6 +272,8 @@ static int ionic_setup_one(struct ionic *ionic) 
	}

	ionic_debugfs_add_ident(ionic);



	ionic_map_cmb(ionic);



	err = ionic_init(ionic);

	if (err) {

		dev_err(dev, "Cannot init device: %d, aborting\n", err);

drivers/net/ethernet/pensando/ionic/ionic_dev.c

+255 −15
Original line number Diff line number Diff line
@@ -199,13 +199,201 @@ void ionic_init_devinfo(struct ionic *ionic) 
	dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version);

}



static void ionic_map_disc_cmb(struct ionic *ionic)

{

	struct ionic_identity *ident = &ionic->ident;

	u32 length_reg0, length, offset, num_regions;

	struct ionic_dev_bar *bar = ionic->bars;

	struct ionic_dev *idev = &ionic->idev;

	struct device *dev = ionic->dev;

	int err, sz, i;

	u64 end;



	mutex_lock(&ionic->dev_cmd_lock);



	ionic_dev_cmd_discover_cmb(idev);

	err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);

	if (!err) {

		sz = min(sizeof(ident->cmb_layout),

			 sizeof(idev->dev_cmd_regs->data));

		memcpy_fromio(&ident->cmb_layout,

			      &idev->dev_cmd_regs->data, sz);

	}

	mutex_unlock(&ionic->dev_cmd_lock);



	if (err) {

		dev_warn(dev, "Cannot discover CMB layout, disabling CMB\n");

		return;

	}



	bar += 2;



	num_regions = le32_to_cpu(ident->cmb_layout.num_regions);

	if (!num_regions || num_regions > IONIC_MAX_CMB_REGIONS) {

		dev_warn(dev, "Invalid number of CMB entries (%d)\n",

			 num_regions);

		return;

	}



	dev_dbg(dev, "ionic_cmb_layout_identity num_regions %d flags %x:\n",

		num_regions, ident->cmb_layout.flags);



	for (i = 0; i < num_regions; i++) {

		offset = le32_to_cpu(ident->cmb_layout.region[i].offset);

		length = le32_to_cpu(ident->cmb_layout.region[i].length);

		end = offset + length;



		dev_dbg(dev, "CMB entry %d: bar_num %u cmb_type %u offset %x length %u\n",

			i, ident->cmb_layout.region[i].bar_num,

			ident->cmb_layout.region[i].cmb_type,

			offset, length);



		if (end > (bar->len >> IONIC_CMB_SHIFT_64K)) {

			dev_warn(dev, "Out of bounds CMB region %d offset %x length %u\n",

				 i, offset, length);

			return;

		}

	}



	/* if first entry matches PCI config, expdb is not supported */

	if (ident->cmb_layout.region[0].bar_num == bar->res_index &&

	    le32_to_cpu(ident->cmb_layout.region[0].length) == bar->len &&

	    !ident->cmb_layout.region[0].offset) {

		dev_warn(dev, "No CMB mapping discovered\n");

		return;

	}



	/* process first entry for regular mapping */

	length_reg0 = le32_to_cpu(ident->cmb_layout.region[0].length);

	if (!length_reg0) {

		dev_warn(dev, "region len = 0. No CMB mapping discovered\n");

		return;

	}



	/* Verify first entry size matches expected 8MB size (in 64KB pages) */

	if (length_reg0 != IONIC_BAR2_CMB_ENTRY_SIZE >> IONIC_CMB_SHIFT_64K) {

		dev_warn(dev, "Unexpected CMB size in entry 0: %u pages\n",

			 length_reg0);

		return;

	}



	sz = BITS_TO_LONGS((length_reg0 << IONIC_CMB_SHIFT_64K) /

			    PAGE_SIZE) * sizeof(long);

	idev->cmb_inuse = kzalloc(sz, GFP_KERNEL);

	if (!idev->cmb_inuse) {

		dev_warn(dev, "No memory for CMB, disabling\n");

		idev->phy_cmb_pages = 0;

		idev->phy_cmb_expdb64_pages = 0;

		idev->phy_cmb_expdb128_pages = 0;

		idev->phy_cmb_expdb256_pages = 0;

		idev->phy_cmb_expdb512_pages = 0;

		idev->cmb_npages = 0;

		return;

	}



	for (i = 0; i < num_regions; i++) {

		/* check this region matches first region length as to

		 * ease implementation

		 */

		if (le32_to_cpu(ident->cmb_layout.region[i].length) !=

		    length_reg0)

			continue;



		offset = le32_to_cpu(ident->cmb_layout.region[i].offset);



		switch (ident->cmb_layout.region[i].cmb_type) {

		case IONIC_CMB_TYPE_DEVMEM:

			idev->phy_cmb_pages = bar->bus_addr + offset;

			idev->cmb_npages =

			    (length_reg0 << IONIC_CMB_SHIFT_64K) / PAGE_SIZE;

			dev_dbg(dev, "regular cmb mapping: bar->bus_addr %pa region[%d].length %u\n",

				&bar->bus_addr, i, length);

			dev_dbg(dev, "idev->phy_cmb_pages %pad, idev->cmb_npages %u\n",

				&idev->phy_cmb_pages, idev->cmb_npages);

			break;



		case IONIC_CMB_TYPE_EXPDB64:

			idev->phy_cmb_expdb64_pages =

				bar->bus_addr + (offset << IONIC_CMB_SHIFT_64K);

			dev_dbg(dev, "idev->phy_cmb_expdb64_pages %pad\n",

				&idev->phy_cmb_expdb64_pages);

			break;



		case IONIC_CMB_TYPE_EXPDB128:

			idev->phy_cmb_expdb128_pages =

				bar->bus_addr + (offset << IONIC_CMB_SHIFT_64K);

			dev_dbg(dev, "idev->phy_cmb_expdb128_pages %pad\n",

				&idev->phy_cmb_expdb128_pages);

			break;



		case IONIC_CMB_TYPE_EXPDB256:

			idev->phy_cmb_expdb256_pages =

				bar->bus_addr + (offset << IONIC_CMB_SHIFT_64K);

			dev_dbg(dev, "idev->phy_cmb_expdb256_pages %pad\n",

				&idev->phy_cmb_expdb256_pages);

			break;



		case IONIC_CMB_TYPE_EXPDB512:

			idev->phy_cmb_expdb512_pages =

				bar->bus_addr + (offset << IONIC_CMB_SHIFT_64K);

			dev_dbg(dev, "idev->phy_cmb_expdb512_pages %pad\n",

				&idev->phy_cmb_expdb512_pages);

			break;



		default:

			dev_warn(dev, "[%d] Invalid cmb_type (%d)\n",

				 i, ident->cmb_layout.region[i].cmb_type);

			break;

		}

	}

}



static void ionic_map_classic_cmb(struct ionic *ionic)

{

	struct ionic_dev_bar *bar = ionic->bars;

	struct ionic_dev *idev = &ionic->idev;

	struct device *dev = ionic->dev;

	int sz;



	bar += 2;

	/* classic CMB mapping */

	idev->phy_cmb_pages = bar->bus_addr;

	idev->cmb_npages = bar->len / PAGE_SIZE;

	dev_dbg(dev, "classic cmb mapping: bar->bus_addr %pa bar->len %lu\n",

		&bar->bus_addr, bar->len);

	dev_dbg(dev, "idev->phy_cmb_pages %pad, idev->cmb_npages %u\n",

		&idev->phy_cmb_pages, idev->cmb_npages);



	sz = BITS_TO_LONGS(idev->cmb_npages) * sizeof(long);

	idev->cmb_inuse = kzalloc(sz, GFP_KERNEL);

	if (!idev->cmb_inuse) {

		idev->phy_cmb_pages = 0;

		idev->cmb_npages = 0;

	}

}



void ionic_map_cmb(struct ionic *ionic)

{

	struct pci_dev *pdev = ionic->pdev;

	struct device *dev = ionic->dev;



	if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM)) {

		dev_dbg(dev, "No CMB, disabling\n");

		return;

	}



	if (ionic->ident.dev.capabilities & cpu_to_le64(IONIC_DEV_CAP_DISC_CMB))

		ionic_map_disc_cmb(ionic);

	else

		ionic_map_classic_cmb(ionic);

}



int ionic_dev_setup(struct ionic *ionic)

{

	struct ionic_dev_bar *bar = ionic->bars;

	unsigned int num_bars = ionic->num_bars;

	struct ionic_dev *idev = &ionic->idev;

	struct device *dev = ionic->dev;

	int size;

	u32 sig;

	int err;
@@ -255,16 +443,11 @@ int ionic_dev_setup(struct ionic *ionic) 
	mutex_init(&idev->cmb_inuse_lock);

	if (num_bars < 3 || !ionic->bars[IONIC_PCI_BAR_CMB].len) {

		idev->cmb_inuse = NULL;

		idev->phy_cmb_pages = 0;

		idev->cmb_npages = 0;

		return 0;

	}



	idev->phy_cmb_pages = bar->bus_addr;

	idev->cmb_npages = bar->len / PAGE_SIZE;

	size = BITS_TO_LONGS(idev->cmb_npages) * sizeof(long);

	idev->cmb_inuse = kzalloc(size, GFP_KERNEL);

	if (!idev->cmb_inuse)

		dev_warn(dev, "No memory for CMB, disabling\n");



	return 0;

}
@@ -277,6 +460,11 @@ void ionic_dev_teardown(struct ionic *ionic) 
	idev->phy_cmb_pages = 0;

	idev->cmb_npages = 0;



	idev->phy_cmb_expdb64_pages = 0;

	idev->phy_cmb_expdb128_pages = 0;

	idev->phy_cmb_expdb256_pages = 0;

	idev->phy_cmb_expdb512_pages = 0;



	if (ionic->wq) {

		destroy_workqueue(ionic->wq);

		ionic->wq = NULL;
@@ -698,28 +886,79 @@ void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 
	ionic_dev_cmd_go(idev, &cmd);

}



void ionic_dev_cmd_discover_cmb(struct ionic_dev *idev)

{

	union ionic_dev_cmd cmd = {

		.discover_cmb.opcode = IONIC_CMD_DISCOVER_CMB,

	};



	ionic_dev_cmd_go(idev, &cmd);

}



int ionic_db_page_num(struct ionic_lif *lif, int pid)

{

	return (lif->hw_index * lif->dbid_count) + pid;

}



int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order)

int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr,

		  int order, u8 stride_log2, bool *expdb)

{

	struct ionic_dev *idev = &lif->ionic->idev;

	int ret;

	void __iomem *nonexpdb_pgptr;

	phys_addr_t nonexpdb_pgaddr;

	int i, idx;



	mutex_lock(&idev->cmb_inuse_lock);

	ret = bitmap_find_free_region(idev->cmb_inuse, idev->cmb_npages, order);

	idx = bitmap_find_free_region(idev->cmb_inuse, idev->cmb_npages, order);

	mutex_unlock(&idev->cmb_inuse_lock);



	if (ret < 0)

		return ret;



	*pgid = ret;

	*pgaddr = idev->phy_cmb_pages + ret * PAGE_SIZE;

	if (idx < 0)

		return idx;



	*pgid = (u32)idx;



	if (idev->phy_cmb_expdb64_pages &&

	    stride_log2 == IONIC_EXPDB_64B_WQE_LG2) {

		*pgaddr = idev->phy_cmb_expdb64_pages + idx * PAGE_SIZE;

		if (expdb)

			*expdb = true;

	} else if (idev->phy_cmb_expdb128_pages &&

		  stride_log2 == IONIC_EXPDB_128B_WQE_LG2) {

		*pgaddr = idev->phy_cmb_expdb128_pages + idx * PAGE_SIZE;

		if (expdb)

			*expdb = true;

	} else if (idev->phy_cmb_expdb256_pages &&

		  stride_log2 == IONIC_EXPDB_256B_WQE_LG2) {

		*pgaddr = idev->phy_cmb_expdb256_pages + idx * PAGE_SIZE;

		if (expdb)

			*expdb = true;

	} else if (idev->phy_cmb_expdb512_pages &&

		  stride_log2 == IONIC_EXPDB_512B_WQE_LG2) {

		*pgaddr = idev->phy_cmb_expdb512_pages + idx * PAGE_SIZE;

		if (expdb)

			*expdb = true;

	} else {

		*pgaddr = idev->phy_cmb_pages + idx * PAGE_SIZE;

		if (expdb)

			*expdb = false;

	}



	/* clear the requested CMB region, 1 PAGE_SIZE ioremap at a time */

	nonexpdb_pgaddr = idev->phy_cmb_pages + idx * PAGE_SIZE;

	for (i = 0; i < (1 << order); i++) {

		nonexpdb_pgptr =

			ioremap_wc(nonexpdb_pgaddr + i * PAGE_SIZE, PAGE_SIZE);

		if (!nonexpdb_pgptr) {

			ionic_put_cmb(lif, *pgid, order);

			return -ENOMEM;

		}

		memset_io(nonexpdb_pgptr, 0, PAGE_SIZE);

		iounmap(nonexpdb_pgptr);

	}



	return 0;

}

EXPORT_SYMBOL_NS(ionic_get_cmb, "NET_IONIC");



void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order)

{
@@ -729,6 +968,7 @@ void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order) 
	bitmap_release_region(idev->cmb_inuse, pgid, order);

	mutex_unlock(&idev->cmb_inuse_lock);

}

EXPORT_SYMBOL_NS(ionic_put_cmb, "NET_IONIC");



int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,

		  struct ionic_intr_info *intr,

drivers/net/ethernet/pensando/ionic/ionic_dev.h

+12 −2
Original line number Diff line number Diff line
@@ -35,6 +35,11 @@ 
#define IONIC_RX_MIN_DOORBELL_DEADLINE	(HZ / 100)	/* 10ms */

#define IONIC_RX_MAX_DOORBELL_DEADLINE	(HZ * 4)	/* 4s */



#define IONIC_EXPDB_64B_WQE_LG2		6

#define IONIC_EXPDB_128B_WQE_LG2	7

#define IONIC_EXPDB_256B_WQE_LG2	8

#define IONIC_EXPDB_512B_WQE_LG2	9



struct ionic_dev_bar {

	void __iomem *vaddr;

	phys_addr_t bus_addr;
@@ -171,6 +176,11 @@ struct ionic_dev { 
	dma_addr_t phy_cmb_pages;

	u32 cmb_npages;



	dma_addr_t phy_cmb_expdb64_pages;

	dma_addr_t phy_cmb_expdb128_pages;

	dma_addr_t phy_cmb_expdb256_pages;

	dma_addr_t phy_cmb_expdb512_pages;



	u32 port_info_sz;

	struct ionic_port_info *port_info;

	dma_addr_t port_info_pa;
@@ -351,8 +361,8 @@ void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 


int ionic_db_page_num(struct ionic_lif *lif, int pid);



int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order);

void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order);

void ionic_dev_cmd_discover_cmb(struct ionic_dev *idev);

void ionic_map_cmb(struct ionic *ionic);



int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,

		  struct ionic_intr_info *intr,

drivers/net/ethernet/pensando/ionic/ionic_if.h

+89 −0
Original line number Diff line number Diff line
@@ -56,6 +56,9 @@ enum ionic_cmd_opcode { 
	IONIC_CMD_VF_SETATTR			= 61,

	IONIC_CMD_VF_CTRL			= 62,



	/* CMB command */

	IONIC_CMD_DISCOVER_CMB			= 80,



	/* QoS commands */

	IONIC_CMD_QOS_CLASS_IDENTIFY		= 240,

	IONIC_CMD_QOS_CLASS_INIT		= 241,
@@ -269,9 +272,11 @@ union ionic_drv_identity { 
/**

 * enum ionic_dev_capability - Device capabilities

 * @IONIC_DEV_CAP_VF_CTRL:     Device supports VF ctrl operations

 * @IONIC_DEV_CAP_DISC_CMB:    Device supports CMB discovery operations

 */

enum ionic_dev_capability {

	IONIC_DEV_CAP_VF_CTRL        = BIT(0),

	IONIC_DEV_CAP_DISC_CMB       = BIT(1),

};



/**
@@ -395,6 +400,7 @@ enum ionic_logical_qtype { 
 * @IONIC_Q_F_4X_DESC:      Quadruple main descriptor size

 * @IONIC_Q_F_4X_CQ_DESC:   Quadruple cq descriptor size

 * @IONIC_Q_F_4X_SG_DESC:   Quadruple sg descriptor size

 * @IONIC_QIDENT_F_EXPDB:   Queue supports express doorbell

 */

enum ionic_q_feature {

	IONIC_QIDENT_F_CQ		= BIT_ULL(0),
@@ -407,6 +413,7 @@ enum ionic_q_feature { 
	IONIC_Q_F_4X_DESC		= BIT_ULL(7),

	IONIC_Q_F_4X_CQ_DESC		= BIT_ULL(8),

	IONIC_Q_F_4X_SG_DESC		= BIT_ULL(9),

	IONIC_QIDENT_F_EXPDB		= BIT_ULL(10),

};



/**
@@ -2213,6 +2220,80 @@ struct ionic_vf_ctrl_comp { 
	u8      rsvd[15];

};



/**

 * struct ionic_discover_cmb_cmd - CMB discovery command

 * @opcode: Opcode for the command

 * @rsvd:   Reserved bytes

 */

struct ionic_discover_cmb_cmd {

	u8	opcode;

	u8	rsvd[63];

};



/**

 * struct ionic_discover_cmb_comp - CMB discover command completion.

 * @status: Status of the command (enum ionic_status_code)

 * @rsvd:   Reserved bytes

 */

struct ionic_discover_cmb_comp {

	u8	status;

	u8	rsvd[15];

};



#define IONIC_MAX_CMB_REGIONS	16

#define IONIC_CMB_SHIFT_64K	16



enum ionic_cmb_type {

	IONIC_CMB_TYPE_DEVMEM	= 0,

	IONIC_CMB_TYPE_EXPDB64	= 1,

	IONIC_CMB_TYPE_EXPDB128	= 2,

	IONIC_CMB_TYPE_EXPDB256	= 3,

	IONIC_CMB_TYPE_EXPDB512	= 4,

};



/**

 * union ionic_cmb_region - Configuration for CMB region

 * @bar_num:	CMB mapping number from FW

 * @cmb_type:	Type of CMB this region describes (enum ionic_cmb_type)

 * @rsvd:	Reserved

 * @offset:	Offset within BAR in 64KB pages

 * @length:	Length of the CMB region

 * @words:	32-bit words for direct access to the entire region

 */

union ionic_cmb_region {

	struct {

		u8	bar_num;

		u8	cmb_type;

		u8	rsvd[6];

		__le32	offset;

		__le32	length;

	} __packed;

	__le32  words[4];

};



/**

 * union ionic_discover_cmb_identity - CMB layout identity structure

 * @num_regions:    Number of CMB regions, up to 16

 * @flags:          Feature and capability bits (0 for express

 *                  doorbell, 1 for 4K alignment indicator,

 *                  31-24 for version information)

 * @region:         CMB mappings region, entry 0 for regular

 *                  mapping, entries 1-7 for WQE sizes 64,

 *                  128, 256, 512, 1024, 2048 and 4096 bytes

 * @words:          Full union buffer size

 */

union ionic_discover_cmb_identity {

	struct {

		__le32 num_regions;

#define IONIC_CMB_FLAG_EXPDB	BIT(0)

#define IONIC_CMB_FLAG_4KALIGN	BIT(1)

#define IONIC_CMB_FLAG_VERSION	0xff000000

		__le32 flags;

		union ionic_cmb_region region[IONIC_MAX_CMB_REGIONS];

	};

	__le32 words[478];

};



/**

 * struct ionic_qos_identify_cmd - QoS identify command

 * @opcode:  opcode
@@ -3073,6 +3154,8 @@ union ionic_dev_cmd { 
	struct ionic_vf_getattr_cmd vf_getattr;

	struct ionic_vf_ctrl_cmd vf_ctrl;



	struct ionic_discover_cmb_cmd discover_cmb;



	struct ionic_lif_identify_cmd lif_identify;

	struct ionic_lif_init_cmd lif_init;

	struct ionic_lif_reset_cmd lif_reset;
@@ -3112,6 +3195,8 @@ union ionic_dev_cmd_comp { 
	struct ionic_vf_getattr_comp vf_getattr;

	struct ionic_vf_ctrl_comp vf_ctrl;



	struct ionic_discover_cmb_comp discover_cmb;



	struct ionic_lif_identify_comp lif_identify;

	struct ionic_lif_init_comp lif_init;

	ionic_lif_reset_comp lif_reset;
@@ -3253,6 +3338,9 @@ union ionic_adminq_comp { 
#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET	0x0c00

#define IONIC_BAR0_INTR_STATUS_OFFSET		0x1000

#define IONIC_BAR0_INTR_CTRL_OFFSET		0x2000



/* BAR2 */

#define IONIC_BAR2_CMB_ENTRY_SIZE		0x800000

#define IONIC_DEV_CMD_DONE			0x00000001



#define IONIC_ASIC_TYPE_NONE			0
@@ -3306,6 +3394,7 @@ struct ionic_identity { 
	union ionic_port_identity port;

	union ionic_qos_identity qos;

	union ionic_q_identity txq;

	union ionic_discover_cmb_identity cmb_layout;

};



#endif /* _IONIC_IF_H_ */