Unverified Commit 1129c001 authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: cs-amp-lib: Some bug and typo fixes 

Richard Fitzgerald <rf@opensource.cirrus.com> says:

This series fixes bugs and a typo in cs-amp-lib.

Link: https://patch.msgid.link/20260521122511.987322-1-rf@opensource.cirrus.com
parents 18e7bd9f a6852526

.mailmap

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@@ -857,6 +857,7 @@ Tobias Klauser <tklauser@distanz.ch> <klto@zhaw.ch> 
Tobias Klauser <tklauser@distanz.ch> <tklauser@nuerscht.ch>

Tobias Klauser <tklauser@distanz.ch> <tklauser@xenon.tklauser.home>

Todor Tomov <todor.too@gmail.com> <todor.tomov@linaro.org>

Tomasz Jeznach <tomasz.jeznach@linux.dev> <tjeznach@rivosinc.com>

Tony Luck <tony.luck@intel.com>

Trilok Soni <quic_tsoni@quicinc.com> <tsoni@codeaurora.org>

TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>

Documentation/arch/riscv/cmodx.rst

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@@ -21,13 +21,13 @@ call at each patchable function entry, and patches it dynamically at runtime to 
enable or disable the redirection. In the case of RISC-V, 2 instructions,

AUIPC + JALR, are required to compose a function call. However, it is impossible

to patch 2 instructions and expect that a concurrent read-side executes them

without a race condition. This series makes atmoic code patching possible in

without a race condition. This series makes atomic code patching possible in

RISC-V ftrace. Kernel preemption makes things even worse as it allows the old

state to persist across the patching process with stop_machine().



In order to get rid of stop_machine() and run dynamic ftrace with full kernel

preemption, we partially initialize each patchable function entry at boot-time,

setting the first instruction to AUIPC, and the second to NOP. Now, atmoic

setting the first instruction to AUIPC, and the second to NOP. Now, atomic

patching is possible because the kernel only has to update one instruction.

According to Ziccif, as long as an instruction is naturally aligned, the ISA

guarantee an  atomic update.
@@ -36,8 +36,8 @@ By fixing down the first instruction, AUIPC, the range of the ftrace trampoline 
is limited to +-2K from the predetermined target, ftrace_caller, due to the lack

of immediate encoding space in RISC-V. To address the issue, we introduce

CALL_OPS, where an 8B naturally align metadata is added in front of each

pacthable function. The metadata is resolved at the first trampoline, then the

execution can be derect to another custom trampoline.

patchable function. The metadata is resolved at the first trampoline, then the

execution can be directed to another custom trampoline.



CMODX in the User Space

-----------------------

Documentation/arch/riscv/zicfilp.rst

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@@ -78,7 +78,7 @@ the program. 


Per-task indirect branch tracking state can be monitored and

controlled via the :c:macro:`PR_GET_CFI` and :c:macro:`PR_SET_CFI`

``prctl()` arguments (respectively), by supplying

``prctl()`` arguments (respectively), by supplying

:c:macro:`PR_CFI_BRANCH_LANDING_PADS` as the second argument.  These

are architecture-agnostic, and will return -EINVAL if the underlying

functionality is not supported.

Documentation/hwmon/sy7636a-hwmon.rst

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@@ -22,5 +22,5 @@ The following sensors are supported 
sysfs-Interface

---------------



temp0_input

temp1_input

	- Temperature of external NTC (milli-degree C)

Documentation/netlink/genetlink-c.yaml

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@@ -69,6 +69,15 @@ properties: 
        header:

          description: For C-compatible languages, header which already defines this value.

          type: string

        scope:

          description: |

            Visibility of this definition. "uapi" (default) renders into

            the uAPI header, "kernel" renders into the kernel-side

            generated header, "user" renders into the user-side

            generated header. When combined with `header:`, the

            definition is not rendered, and the named header is

            included only by code matching the scope.

          enum: [ uapi, kernel, user ]

        type:

          enum: [ const, enum, flags ]

        doc: