Commit 11382d02 authored by Li Ma's avatar Li Ma Committed by Alex Deucher
Browse files

drm/amd/pm: smu v14.0.4 reuse smu v14.0.0 dpmtable 



Replace IP VERSION with smu->is_apu in if condition.
And the dpmtable of smu v14.0.4 is same as smu v14.0.0.

Signed-off-by: default avatarLi Ma <li.ma@amd.com>
Reviewed-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9cd2ad14

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

+6 −12
Original line number Diff line number Diff line
@@ -136,8 +136,7 @@ int smu_v14_0_load_microcode(struct smu_context *smu) 
		    1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);



	for (i = 0; i < adev->usec_timeout; i++) {

		if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||

			amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

		if (smu->is_apu)

			mp1_fw_flags = RREG32_PCIE(MP1_Public |

						   (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));

		else
@@ -210,8 +209,7 @@ int smu_v14_0_check_fw_status(struct smu_context *smu) 
	struct amdgpu_device *adev = smu->adev;

	uint32_t mp1_fw_flags;



	if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||

		amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

	if (smu->is_apu)

		mp1_fw_flags = RREG32_PCIE(MP1_Public |

					   (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));

	else
@@ -866,8 +864,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev, 
		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);



		/* For MP1 SW irqs */

		if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||

			amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {

		if (smu->is_apu) {

			val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);

			val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

			WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
@@ -900,8 +897,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev, 
		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);



		/* For MP1 SW irqs */

		if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||

			amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {

		if (smu->is_apu) {

			val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);

			val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

			val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
@@ -1494,8 +1490,7 @@ int smu_v14_0_set_vcn_enable(struct smu_context *smu, 
		if (adev->vcn.harvest_config & (1 << i))

			continue;



		if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||

		    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {

		if (smu->is_apu) {

			if (i == 0)

				ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

								      SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
@@ -1527,8 +1522,7 @@ int smu_v14_0_set_jpeg_enable(struct smu_context *smu, 
		if (adev->jpeg.harvest_config & (1 << i))

			continue;



		if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||

		    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {

		if (smu->is_apu) {

			if (i == 0)

				ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

								      SMU_MSG_PowerUpJpeg0 : SMU_MSG_PowerDownJpeg0,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

+15 −15
Original line number Diff line number Diff line
@@ -723,10 +723,10 @@ static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context *smu, 
						uint32_t dpm_level,

						uint32_t *freq)

{

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))

		smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);

	else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

		smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);

	else

		smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);



	return 0;

}
@@ -999,10 +999,10 @@ static int smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu, 
							uint32_t *min,

							uint32_t *max)

{

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))

		smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);

	else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

		smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);

	else

		smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);



	return 0;

}
@@ -1104,10 +1104,10 @@ static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu, 
					   enum smu_clk_type clk_type,

					   uint32_t *count)

{

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))

		smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);

	else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

		smu_v14_0_1_get_dpm_level_count(smu, clk_type, count);

	else

		smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);



	return 0;

}
@@ -1372,10 +1372,10 @@ static int smu_v14_0_0_set_fine_grain_gfx_freq_parameters(struct smu_context *sm 


static int smu_v14_0_common_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)

{

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))

		smu_v14_0_0_set_fine_grain_gfx_freq_parameters(smu);

	else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

		smu_v14_0_1_set_fine_grain_gfx_freq_parameters(smu);

	else

		smu_v14_0_0_set_fine_grain_gfx_freq_parameters(smu);



	return 0;

}
@@ -1436,10 +1436,10 @@ static int smu_14_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks * 


static int smu_v14_0_common_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)

{

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))

		smu_14_0_0_get_dpm_table(smu, clock_table);

	else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))

		smu_14_0_1_get_dpm_table(smu, clock_table);

	else

		smu_14_0_0_get_dpm_table(smu, clock_table);



	return 0;

}