Commit 11abb4e8 authored by Joakim Zhang's avatar Joakim Zhang Committed by Will Deacon
Browse files

perf/imx_ddr: Add support for PMU in DB (system interconnects) 



There is a PMU in DB, which has the same function with PMU in DDR
subsystem, the difference is PMU in DB only supports cycles, axid-read,
axid-write events.

e.g.
perf stat -a -e imx8_db0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd
perf stat -a -e imx8_db0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd

Signed-off-by: default avatarJoakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 037e8cf6

drivers/perf/fsl_imx8_ddr_perf.c

+60 −7
Original line number Diff line number Diff line
@@ -53,18 +53,27 @@ 
#define to_ddr_pmu(p)		container_of(p, struct ddr_pmu, pmu)



#define DDR_PERF_DEV_NAME	"imx8_ddr"

#define DB_PERF_DEV_NAME	"imx8_db"

#define DDR_CPUHP_CB_NAME	DDR_PERF_DEV_NAME "_perf_pmu"



static DEFINE_IDA(ddr_ida);

static DEFINE_IDA(db_ida);



/* DDR Perf hardware feature */

#define DDR_CAP_AXI_ID_FILTER			0x1     /* support AXI ID filter */

#define DDR_CAP_AXI_ID_FILTER_ENHANCED		0x3     /* support enhanced AXI ID filter */

#define DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER	0x4	/* support AXI ID PORT CHANNEL filter */



/* Perf type */

enum fsl_ddr_type {

	DDR_PERF_TYPE = 0,	/* ddr Perf (default) */

	DB_PERF_TYPE,		/* db Perf */

};



struct fsl_ddr_devtype_data {

	unsigned int quirks;    /* quirks needed for different DDR Perf core */

	const char *identifier;	/* system PMU identifier for userspace */

	enum fsl_ddr_type type;	/* types of Perf, ddr or db */

};



static const struct fsl_ddr_devtype_data imx8_devtype_data;
@@ -98,6 +107,12 @@ static const struct fsl_ddr_devtype_data imx8dxl_devtype_data = { 
	.identifier = "i.MX8DXL",

};



static const struct fsl_ddr_devtype_data imx8dxl_db_devtype_data = {

	.quirks = DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER,

	.identifier = "i.MX8DXL",

	.type = DB_PERF_TYPE,

};



static const struct of_device_id imx_ddr_pmu_dt_ids[] = {

	{ .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},

	{ .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
@@ -106,6 +121,7 @@ static const struct of_device_id imx_ddr_pmu_dt_ids[] = { 
	{ .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},

	{ .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},

	{ .compatible = "fsl,imx8dxl-ddr-pmu", .data = &imx8dxl_devtype_data},

	{ .compatible = "fsl,imx8dxl-db-pmu", .data = &imx8dxl_db_devtype_data},

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
@@ -285,9 +301,37 @@ static struct attribute *ddr_perf_events_attrs[] = { 
	NULL,

};



static const int ddr_perf_db_visible_event_list[] = {

	EVENT_CYCLES_ID,

	0x41,

	0x42,

};



static umode_t ddr_perf_events_attrs_is_visible(struct kobject *kobj,

						struct attribute *attr, int n)

{

	struct device *dev = kobj_to_dev(kobj);

	struct ddr_pmu *pmu = dev_get_drvdata(dev);

	struct perf_pmu_events_attr *pmu_attr;

	unsigned int i;



	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);



	if (pmu->devtype_data->type == DDR_PERF_TYPE)

		return attr->mode;



	/* DB Type */

	for (i = 0; i < ARRAY_SIZE(ddr_perf_db_visible_event_list); i++)

		if (pmu_attr->id == ddr_perf_db_visible_event_list[i])

			return attr->mode;



	return 0;

}



static const struct attribute_group ddr_perf_events_attr_group = {

	.name = "events",

	.attrs = ddr_perf_events_attrs,

	.is_visible = ddr_perf_events_attrs_is_visible,

};



PMU_FORMAT_ATTR(event, "config:0-7");
@@ -737,6 +781,7 @@ static int ddr_perf_probe(struct platform_device *pdev) 
	struct ddr_pmu *pmu;

	struct device_node *np;

	void __iomem *base;

	struct ida *ida;

	char *name;

	int nclks;

	int num;
@@ -761,21 +806,25 @@ static int ddr_perf_probe(struct platform_device *pdev) 
	if (nclks < 0)

		return dev_err_probe(&pdev->dev, nclks, "Failure get clks\n");



	num = ida_alloc(&ddr_ida, GFP_KERNEL);

	pmu->devtype_data = of_device_get_match_data(&pdev->dev);



	ida = pmu->devtype_data->type == DDR_PERF_TYPE ? &ddr_ida : &db_ida;

	num = ida_alloc(ida, GFP_KERNEL);

	if (num < 0)

		return num;



	pmu->id = num;



	name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d",

			      num);

	if (pmu->devtype_data->type == DDR_PERF_TYPE)

		name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", num);

	else

		name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DB_PERF_DEV_NAME "%d", num);



	if (!name) {

		ret = -ENOMEM;

		goto idr_free;

	}



	pmu->devtype_data = of_device_get_match_data(&pdev->dev);



	pmu->cpu = raw_smp_processor_id();

	ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,

				      DDR_CPUHP_CB_NAME,
@@ -832,7 +881,7 @@ static int ddr_perf_probe(struct platform_device *pdev) 
cpuhp_instance_err:

	cpuhp_remove_multi_state(pmu->cpuhp_state);

idr_free:

	ida_free(&ddr_ida, pmu->id);

	ida_free(ida, pmu->id);

	dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret);

	return ret;

}
@@ -846,7 +895,11 @@ static void ddr_perf_remove(struct platform_device *pdev) 


	perf_pmu_unregister(&pmu->pmu);



	if (pmu->devtype_data->type == DDR_PERF_TYPE)

		ida_free(&ddr_ida, pmu->id);

	else

		ida_free(&db_ida, pmu->id);



}



static struct platform_driver imx_ddr_pmu_driver = {