Commit 12e5df81 authored by Candice Li's avatar Candice Li Committed by Alex Deucher
Browse files

drm/amdgpu: Add nps_mode in RAS init_flag 



Add nps_mode in RAS init_flag.

Signed-off-by: default avatarCandice Li <candice.li@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d2e3961a

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+3 −0
Original line number Diff line number Diff line
@@ -1834,6 +1834,9 @@ int psp_ras_initialize(struct psp_context *psp) 
	ras_cmd->ras_in_message.init_flags.xcc_mask =

		adev->gfx.xcc_mask;

	ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;

	if (adev->gmc.gmc_funcs->query_mem_partition_mode)

		ras_cmd->ras_in_message.init_flags.nps_mode =

			adev->gmc.gmc_funcs->query_mem_partition_mode(adev);



	ret = psp_ta_load(psp, &psp->ras_context.context);

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

+9 −0
Original line number Diff line number Diff line
@@ -113,6 +113,14 @@ enum ta_ras_address_type { 
	TA_RAS_PA_TO_MCA,

};



enum ta_ras_nps_mode {

	TA_RAS_UNKNOWN_MODE = 0,

	TA_RAS_NPS1_MODE = 1,

	TA_RAS_NPS2_MODE = 2,

	TA_RAS_NPS4_MODE = 4,

	TA_RAS_NPS8_MODE = 8,

};



/* Input/output structures for RAS commands */

/**********************************************************/
@@ -139,6 +147,7 @@ struct ta_ras_init_flags { 
	uint8_t dgpu_mode;

	uint16_t xcc_mask;

	uint8_t channel_dis_num;

	uint8_t nps_mode;

};



struct ta_ras_mca_addr {