Commit 132b6228 authored by Andy Yan's avatar Andy Yan Committed by Heiko Stuebner
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clk: rockchip: rk3568: Add PLL rate for 132MHz 



Add PLL rate for 132 MHz to allow raydium-rm67200 panel with
1080x1920 resolution to run at 60 fps that driven by VPLL.

Signed-off-by: default avatarAndy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20250615123922.661998-1-andyshrk@163.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 19272b37

drivers/clk/rockchip/clk-rk3568.c

+1 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { 
	RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),

	RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),

	RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),

	RK3036_PLL_RATE(132000000, 1, 66, 6, 2, 1, 0),

	RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0),

	RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),

	RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),