Commit 1361d755 authored by Ondrej Jirman's avatar Ondrej Jirman Committed by Heiko Stuebner
Browse files

clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent 



Otherwise when when clk_i2s0 muxes to clk_i2s0_div which requires
setting high divider value on clk_i2s0_div, and then muxes back to
clk_i2s0_frac, clk_i2s0_frac would have no way to change the
clk_i2s0_div's divider ratio back to 1 so that it can satisfy the
condition for m/n > 20 for fractional division to work correctly.

Bug is reproducible by playing 44.1k audio, then 48k audio, and then
44.1k audio again. This results in clk_i2s0_div being set to 49 and
clk_i2s0_frac not being able to cope with such a low input clock rate
and audio playing extremely slowly.

The identical issue is on i2s1 and i2s2 clocks, too.

Signed-off-by: default avatarOndrej Jirman <megi@xff.cz>
Link: https://lore.kernel.org/r/20240217193439.1762213-1-megi@xff.cz


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent dae3e570

drivers/clk/rockchip/clk-rk3399.c

+3 −3
Original line number Diff line number Diff line
@@ -597,7 +597,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,

			RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,

			RK3399_CLKGATE_CON(8), 3, GFLAGS),

	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,

	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,

			RK3399_CLKSEL_CON(96), 0,

			RK3399_CLKGATE_CON(8), 4, GFLAGS,

			&rk3399_i2s0_fracmux),
@@ -607,7 +607,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
	COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,

			RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,

			RK3399_CLKGATE_CON(8), 6, GFLAGS),

	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,

	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,

			RK3399_CLKSEL_CON(97), 0,

			RK3399_CLKGATE_CON(8), 7, GFLAGS,

			&rk3399_i2s1_fracmux),
@@ -617,7 +617,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
	COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,

			RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,

			RK3399_CLKGATE_CON(8), 9, GFLAGS),

	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,

	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,

			RK3399_CLKSEL_CON(98), 0,

			RK3399_CLKGATE_CON(8), 10, GFLAGS,

			&rk3399_i2s2_fracmux),