Commit 139f2673 authored by Suraj Kandpal's avatar Suraj Kandpal
Browse files

drm/i915/dpll: Rename intel_shared_dpll_state 



Rename intel_shared_dpll_state to just intel_dpll_state since it may
not necessarily store share dpll state info specially since
DISPLAY_VER >= 14 PLL's are not shared.
Also change the name of variables which may have been associated as
a shared_dpll.

Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20250515071801.2221120-4-suraj.kandpal@intel.com
parent e12c9b43

drivers/gpu/drm/i915/display/intel_display_types.h

+1 −1
Original line number Diff line number Diff line
@@ -595,7 +595,7 @@ struct intel_atomic_state { 


	bool dpll_set, modeset;



	struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];

	struct intel_dpll_state dpll_state[I915_NUM_PLLS];



	struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+28 −28
Original line number Diff line number Diff line
@@ -122,17 +122,17 @@ struct intel_dpll_mgr { 


static void

intel_atomic_duplicate_dpll_state(struct intel_display *display,

				  struct intel_shared_dpll_state *shared_dpll)

				  struct intel_dpll_state *dpll_state)

{

	struct intel_shared_dpll *pll;

	int i;



	/* Copy shared dpll state */

	for_each_shared_dpll(display, pll, i)

		shared_dpll[pll->index] = pll->state;

		dpll_state[pll->index] = pll->state;

}



static struct intel_shared_dpll_state *

static struct intel_dpll_state *

intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)

{

	struct intel_atomic_state *state = to_intel_atomic_state(s);
@@ -144,10 +144,10 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) 
		state->dpll_set = true;



		intel_atomic_duplicate_dpll_state(display,

						  state->shared_dpll);

						  state->dpll_state);

	}



	return state->shared_dpll;

	return state->dpll_state;

}



/**
@@ -365,11 +365,11 @@ intel_find_shared_dpll(struct intel_atomic_state *state, 
{

	struct intel_display *display = to_intel_display(crtc);

	unsigned long dpll_mask_all = intel_dpll_mask_all(display);

	struct intel_shared_dpll_state *shared_dpll;

	struct intel_dpll_state *dpll_state;

	struct intel_shared_dpll *unused_pll = NULL;

	enum intel_dpll_id id;



	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);

	dpll_state = intel_atomic_get_shared_dpll_state(&state->base);



	drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
@@ -381,20 +381,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state, 
			continue;



		/* Only want to check enabled timings first */

		if (shared_dpll[pll->index].pipe_mask == 0) {

		if (dpll_state[pll->index].pipe_mask == 0) {

			if (!unused_pll)

				unused_pll = pll;

			continue;

		}



		if (memcmp(dpll_hw_state,

			   &shared_dpll[pll->index].hw_state,

			   &dpll_state[pll->index].hw_state,

			   sizeof(*dpll_hw_state)) == 0) {

			drm_dbg_kms(display->drm,

				    "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",

				    crtc->base.base.id, crtc->base.name,

				    pll->info->name,

				    shared_dpll[pll->index].pipe_mask,

				    dpll_state[pll->index].pipe_mask,

				    pll->active_mask);

			return pll;

		}
@@ -415,20 +415,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state, 
 * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC

 * @crtc: CRTC on which behalf the reference is taken

 * @pll: DPLL for which the reference is taken

 * @shared_dpll_state: the DPLL atomic state in which the reference is tracked

 * @dpll_state: the DPLL atomic state in which the reference is tracked

 *

 * Take a reference for @pll tracking the use of it by @crtc.

 */

static void

intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,

				 const struct intel_shared_dpll *pll,

				 struct intel_shared_dpll_state *shared_dpll_state)

				 struct intel_dpll_state *dpll_state)

{

	struct intel_display *display = to_intel_display(crtc);



	drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);

	drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);



	shared_dpll_state->pipe_mask |= BIT(crtc->pipe);

	dpll_state->pipe_mask |= BIT(crtc->pipe);



	drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",

		    crtc->base.base.id, crtc->base.name, pll->info->name);
@@ -440,34 +440,34 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, 
			    const struct intel_shared_dpll *pll,

			    const struct intel_dpll_hw_state *dpll_hw_state)

{

	struct intel_shared_dpll_state *shared_dpll;

	struct intel_dpll_state *dpll_state;



	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);

	dpll_state = intel_atomic_get_shared_dpll_state(&state->base);



	if (shared_dpll[pll->index].pipe_mask == 0)

		shared_dpll[pll->index].hw_state = *dpll_hw_state;

	if (dpll_state[pll->index].pipe_mask == 0)

		dpll_state[pll->index].hw_state = *dpll_hw_state;



	intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);

	intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);

}



/**

 * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC

 * @crtc: CRTC on which behalf the reference is dropped

 * @pll: DPLL for which the reference is dropped

 * @shared_dpll_state: the DPLL atomic state in which the reference is tracked

 * @dpll_state: the DPLL atomic state in which the reference is tracked

 *

 * Drop a reference for @pll tracking the end of use of it by @crtc.

 */

void

intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,

				   const struct intel_shared_dpll *pll,

				   struct intel_shared_dpll_state *shared_dpll_state)

				   struct intel_dpll_state *dpll_state)

{

	struct intel_display *display = to_intel_display(crtc);



	drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);

	drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);



	shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);

	dpll_state->pipe_mask &= ~BIT(crtc->pipe);



	drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",

		    crtc->base.base.id, crtc->base.name, pll->info->name);
@@ -477,11 +477,11 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state, 
					  const struct intel_crtc *crtc,

					  const struct intel_shared_dpll *pll)

{

	struct intel_shared_dpll_state *shared_dpll;

	struct intel_dpll_state *dpll_state;



	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);

	dpll_state = intel_atomic_get_shared_dpll_state(&state->base);



	intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);

	intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);

}



static void intel_put_dpll(struct intel_atomic_state *state,
@@ -514,7 +514,7 @@ static void intel_put_dpll(struct intel_atomic_state *state, 
void intel_shared_dpll_swap_state(struct intel_atomic_state *state)

{

	struct intel_display *display = to_intel_display(state);

	struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;

	struct intel_dpll_state *dpll_state = state->dpll_state;

	struct intel_shared_dpll *pll;

	int i;
@@ -522,7 +522,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) 
		return;



	for_each_shared_dpll(display, pll, i)

		swap(pll->state, shared_dpll[pll->index]);

		swap(pll->state, dpll_state[pll->index]);

}



static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

+4 −4
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ struct intel_dpll_hw_state { 
};



/**

 * struct intel_shared_dpll_state - hold the DPLL atomic state

 * struct intel_dpll_state - hold the DPLL atomic state

 *

 * This structure holds an atomic state for the DPLL, that can represent

 * either its current state (in struct &intel_shared_dpll) or a desired
@@ -289,7 +289,7 @@ struct intel_dpll_hw_state { 
 *

 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().

 */

struct intel_shared_dpll_state {

struct intel_dpll_state {

	/**

	 * @pipe_mask: mask of pipes using this DPLL, active or not

	 */
@@ -353,7 +353,7 @@ struct intel_shared_dpll { 
	 * Store the state for the pll, including its hw state

	 * and CRTCs using it.

	 */

	struct intel_shared_dpll_state state;

	struct intel_dpll_state state;



	/**

	 * @index: index for atomic state
@@ -406,7 +406,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state, 
				struct intel_crtc *crtc);

void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,

					const struct intel_shared_dpll *pll,

					struct intel_shared_dpll_state *shared_dpll_state);

					struct intel_dpll_state *shared_dpll_state);

void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,

			      enum icl_port_dpll_id port_dpll_id);

void intel_update_active_dpll(struct intel_atomic_state *state,