Commit 14418ddc authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull crypto updates from Herbert Xu:
 "API:
   - Fix memcpy_sglist to handle partially overlapping SG lists
   - Use memcpy_sglist to replace null skcipher
   - Rename CRYPTO_TESTS to CRYPTO_BENCHMARK
   - Flip CRYPTO_MANAGER_DISABLE_TEST into CRYPTO_SELFTESTS
   - Hide CRYPTO_MANAGER
   - Add delayed freeing of driver crypto_alg structures

  Compression:
   - Allocate large buffers on first use instead of initialisation in scomp
   - Drop destination linearisation buffer in scomp
   - Move scomp stream allocation into acomp
   - Add acomp scatter-gather walker
   - Remove request chaining
   - Add optional async request allocation

  Hashing:
   - Remove request chaining
   - Add optional async request allocation
   - Move partial block handling into API
   - Add ahash support to hmac
   - Fix shash documentation to disallow usage in hard IRQs

  Algorithms:
   - Remove unnecessary SIMD fallback code on x86 and arm/arm64
   - Drop avx10_256 xts(aes)/ctr(aes) on x86
   - Improve avx-512 optimisations for xts(aes)
   - Move chacha arch implementations into lib/crypto
   - Move poly1305 into lib/crypto and drop unused Crypto API algorithm
   - Disable powerpc/poly1305 as it has no SIMD fallback
   - Move sha256 arch implementations into lib/crypto
   - Convert deflate to acomp
   - Set block size correctly in cbcmac

  Drivers:
   - Do not use sg_dma_len before mapping in sun8i-ss
   - Fix warm-reboot failure by making shutdown do more work in qat
   - Add locking in zynqmp-sha
   - Remove cavium/zip
   - Add support for PCI device 0x17D8 to ccp
   - Add qat_6xxx support in qat
   - Add support for RK3576 in rockchip-rng
   - Add support for i.MX8QM in caam

  Others:
   - Fix irq_fpu_usable/kernel_fpu_begin inconsistency during CPU bring-up
   - Add new SEV/SNP platform shutdown API in ccp"

* tag 'v6.16-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (382 commits)
  x86/fpu: Fix irq_fpu_usable() to return false during CPU onlining
  crypto: qat - add missing header inclusion
  crypto: api - Redo lookup on EEXIST
  Revert "crypto: testmgr - Add hash export format testing"
  crypto: marvell/cesa - Do not chain submitted requests
  crypto: powerpc/poly1305 - add depends on BROKEN for now
  Revert "crypto: powerpc/poly1305 - Add SIMD fallback"
  crypto: ccp - Add missing tee info reg for teev2
  crypto: ccp - Add missing bootloader info reg for pspv5
  crypto: sun8i-ce - move fallback ahash_request to the end of the struct
  crypto: octeontx2 - Use dynamic allocated memory region for lmtst
  crypto: octeontx2 - Initialize cptlfs device info once
  crypto: xts - Only add ecb if it is not already there
  crypto: lrw - Only add ecb if it is not already there
  crypto: testmgr - Add hash export format testing
  crypto: testmgr - Use ahash for generic tfm
  crypto: hmac - Add ahash support
  crypto: testmgr - Ignore EEXIST on shash allocation
  crypto: algapi - Add driver template support to crypto_inst_setname
  crypto: shash - Set reqsize in shash_alg
  ...
parents 15d90a5e 2297554f
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@@ -4,7 +4,7 @@ KernelVersion: 6.7
Contact:	qat-linux@intel.com
Description:	(RO) Reports the number of correctable errors detected by the device.

		This attribute is only available for qat_4xxx devices.
		This attribute is only available for qat_4xxx and qat_6xxx devices.

What:		/sys/bus/pci/devices/<BDF>/qat_ras/errors_nonfatal
Date:		January 2024
@@ -12,7 +12,7 @@ KernelVersion: 6.7
Contact:	qat-linux@intel.com
Description:	(RO) Reports the number of non fatal errors detected by the device.

		This attribute is only available for qat_4xxx devices.
		This attribute is only available for qat_4xxx and qat_6xxx devices.

What:		/sys/bus/pci/devices/<BDF>/qat_ras/errors_fatal
Date:		January 2024
@@ -20,7 +20,7 @@ KernelVersion: 6.7
Contact:	qat-linux@intel.com
Description:	(RO) Reports the number of fatal errors detected by the device.

		This attribute is only available for qat_4xxx devices.
		This attribute is only available for qat_4xxx and qat_6xxx devices.

What:		/sys/bus/pci/devices/<BDF>/qat_ras/reset_error_counters
Date:		January 2024
@@ -38,4 +38,4 @@ Description: (WO) Write to resets all error counters of a device.
			# cat /sys/bus/pci/devices/<BDF>/qat_ras/errors_fatal
			0

		This attribute is only available for qat_4xxx devices.
		This attribute is only available for qat_4xxx and qat_6xxx devices.
+38 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/amd,ccp-seattle-v1a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: AMD Cryptographic Coprocessor (ccp)

maintainers:
  - Tom Lendacky <thomas.lendacky@amd.com>

properties:
  compatible:
    const: amd,ccp-seattle-v1a

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  dma-coherent: true

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    crypto@e0100000 {
        compatible = "amd,ccp-seattle-v1a";
        reg = <0xe0100000 0x10000>;
        interrupts = <0 3 4>;
        dma-coherent;
    };
+0 −17
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* AMD Cryptographic Coprocessor driver (ccp)

Required properties:
- compatible: Should be "amd,ccp-seattle-v1a"
- reg: Address and length of the register set for the device
- interrupts: Should contain the CCP interrupt

Optional properties:
- dma-coherent: Present if dma operations are coherent

Example:
	ccp@e0100000 {
		compatible = "amd,ccp-seattle-v1a";
		reg = <0 0xe0100000 0 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <0 3 4>;
	};
+0 −16
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Axis crypto engine with PDMA interface.

Required properties:
- compatible : Should be one of the following strings:
	"axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
	"axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
- reg: Base address and size for the PDMA register area.
- interrupts: Interrupt handle for the PDMA interrupt line.

Example:

crypto@f4264000 {
	compatible = "axis,artpec6-crypto";
	reg = <0xf4264000 0x1000>;
	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
};
+39 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/axis,artpec6-crypto.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Axis ARTPEC6 crypto engine with PDMA interface

maintainers:
  - Lars Persson <lars.persson@axis.com>

properties:
  compatible:
    enum:
      - axis,artpec6-crypto
      - axis,artpec7-crypto

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    crypto@f4264000 {
        compatible = "axis,artpec6-crypto";
        reg = <0xf4264000 0x1000>;
        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
    };
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