Commit 145dfd70 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g077: Propagate rate changes to parent clocks 



Add the CLK_SET_RATE_PARENT flag to divider clock registration so that rate
changes can propagate to parent clocks when needed. This allows the CPG
divider clocks to request rate adjustments from their parent, ensuring
correct frequency scaling and improved flexibility in clock rate selection.

Fixes: 065fe720 ("clk: renesas: Add support for R9A09G077 SoC")
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251028165127.991351-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a40efd07

drivers/clk/renesas/r9a09g077-cpg.c

+2 −2
Original line number Diff line number Diff line
@@ -221,7 +221,7 @@ r9a09g077_cpg_div_clk_register(struct device *dev, 


	if (core->dtable)

		clk_hw = clk_hw_register_divider_table(dev, core->name,

						       parent_name, 0,

						       parent_name, CLK_SET_RATE_PARENT,

						       addr,

						       GET_SHIFT(core->conf),

						       GET_WIDTH(core->conf),
@@ -230,7 +230,7 @@ r9a09g077_cpg_div_clk_register(struct device *dev, 
						       &pub->rmw_lock);

	else

		clk_hw = clk_hw_register_divider(dev, core->name,

						 parent_name, 0,

						 parent_name, CLK_SET_RATE_PARENT,

						 addr,

						 GET_SHIFT(core->conf),

						 GET_WIDTH(core->conf),