Commit 1532594d authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/dt-bindings' 

- Convert mobiveil-pcie.txt to YAML and update 'interrupt-names' and
  'reg-names' (Frank Li)

- Add qcom DT SM8550 and SM8650 optional 'global' interrupt for link events
  (Neil Armstrong)

- Add qcom DT 'compatible' strings for IPQ5424 PCIe controller (Manikanta
  Mylavarapu)

* pci/dt-bindings:
  dt-bindings: PCI: qcom: Document the IPQ5424 PCIe controller
  dt-bindings: PCI: qcom,pcie-sm8550: Document 'global' interrupt
  dt-bindings: PCI: mobiveil: Convert mobiveil-pcie.txt to YAML
parents e321b10b c25b978d

Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt

deleted100644 → 0
+0 −52
Original line number Diff line number Diff line 
NXP Layerscape PCIe Gen4 controller



This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all

the common properties defined in mobiveil-pcie.txt.



Required properties:

- compatible: should contain the platform identifier such as:

  "fsl,lx2160a-pcie"

- reg: base addresses and lengths of the PCIe controller register blocks.

  "csr_axi_slave": Bridge config registers

  "config_axi_slave": PCIe controller registers

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: It could include the following entries:

  "intr": The interrupt that is asserted for controller interrupts

  "aer": Asserted for aer interrupt when chip support the aer interrupt with

	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.

  "pme": Asserted for pme interrupt when chip support the pme interrupt with

	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.

- dma-coherent: Indicates that the hardware IP block can ensure the coherency

  of the data transferred from/to the IP block. This can avoid the software

  cache flush/invalid actions, and improve the performance significantly.

- msi-parent : See the generic MSI binding described in

  Documentation/devicetree/bindings/interrupt-controller/msi.txt.



Example:



	pcie@3400000 {

		compatible = "fsl,lx2160a-pcie";

		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */

		reg-names = "csr_axi_slave", "config_axi_slave";

		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */

			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */

			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */

		interrupt-names = "aer", "pme", "intr";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		apio-wins = <8>;

		ppio-wins = <8>;

		dma-coherent;

		bus-range = <0x0 0xff>;

		msi-parent = <&its>;

		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

	};

Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml

0 → 100644
+173 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mobiveil AXI PCIe Host Bridge



maintainers:

  - Frank Li <Frank Li@nxp.com>



description:

  Mobiveil's GPEX 4.0 is a PCIe Gen4 host bridge IP. This configurable IP

  has up to 8 outbound and inbound windows for address translation.



  NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.



properties:

  compatible:

    enum:

      - fsl,lx2160a-pcie

      - mbvl,gpex40-pcie



  reg:

    items:

      - description: PCIe controller registers

      - description: Bridge config registers

      - description: GPIO registers to control slot power

      - description: MSI registers

    minItems: 2



  reg-names:

    items:

      - const: csr_axi_slave

      - const: config_axi_slave

      - const: gpio_slave

      - const: apb_csr

    minItems: 2



  apio-wins:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      number of requested APIO outbound windows

        1. Config window

        2. Memory window

    default: 2

    maximum: 256



  ppio-wins:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: number of requested PPIO inbound windows

    default: 1

    maximum: 256



  interrupt-controller: true



  "#interrupt-cells":

    const: 1



  interrupts:

    minItems: 1

    maxItems: 3



  interrupt-names:

    minItems: 1

    maxItems: 3



  dma-coherent: true



  msi-parent: true



required:

  - compatible

  - reg

  - reg-names



allOf:

  - $ref: /schemas/pci/pci-host-bridge.yaml#

  - if:

      properties:

        compatible:

          enum:

            - fsl,lx2160a-pcie

    then:

      properties:

        reg:

          maxItems: 2



        reg-names:

          maxItems: 2



        interrupts:

          minItems: 3



        interrupt-names:

          items:

            - const: aer

            - const: pme

            - const: intr

    else:

      properties:

        dma-coherent: false

        msi-parent: false

        interrupts:

          maxItems: 1

        interrupt-names: false



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    pcie@b0000000 {

        compatible = "mbvl,gpex40-pcie";

        reg = <0xb0000000 0x00010000>,

              <0xa0000000 0x00001000>,

              <0xff000000 0x00200000>,

              <0xb0010000 0x00001000>;

        reg-names = "csr_axi_slave",

                    "config_axi_slave",

                    "gpio_slave",

                    "apb_csr";

        ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;

        #address-cells = <3>;

        #size-cells = <2>;

        device_type = "pci";

        apio-wins = <2>;

        ppio-wins = <1>;

        bus-range = <0x00 0xff>;

        interrupt-controller;

        #interrupt-cells = <1>;

        interrupt-parent = <&gic>;

        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-map-mask = <0 0 0 7>;

        interrupt-map = <0 0 0 0 &pci_express 0>,

                        <0 0 0 1 &pci_express 1>,

                        <0 0 0 2 &pci_express 2>,

                        <0 0 0 3 &pci_express 3>;

    };



  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;

        pcie@3400000 {

            compatible = "fsl,lx2160a-pcie";

            reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

                   0x80 0x00000000 0x0 0x00001000>; /* configuration space */

            reg-names = "csr_axi_slave", "config_axi_slave";

            ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;

            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */

                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */

                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */

            interrupt-names = "aer", "pme", "intr";

            #address-cells = <3>;

            #size-cells = <2>;

            device_type = "pci";

            apio-wins = <8>;

            ppio-wins = <8>;

            dma-coherent;

            bus-range = <0x00 0xff>;

            msi-parent = <&its>;

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 7>;

            interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

                            <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

                            <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

                            <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

        };

    };

Documentation/devicetree/bindings/pci/mobiveil-pcie.txt

deleted100644 → 0
+0 −72
Original line number Diff line number Diff line 
* Mobiveil AXI PCIe Root Port Bridge DT description



Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP

has up to 8 outbound and inbound windows for the address translation.



Required properties:

- #address-cells: Address representation for root ports, set to <3>

- #size-cells: Size representation for root ports, set to <2>

- #interrupt-cells: specifies the number of cells needed to encode an

	interrupt source. The value must be 1.

- compatible: Should contain "mbvl,gpex40-pcie"

- reg: Should contain PCIe registers location and length

	Mandatory:

	"config_axi_slave": PCIe controller registers

	"csr_axi_slave"	  : Bridge config registers

	Optional:

	"gpio_slave"	  : GPIO registers to control slot power

	"apb_csr"	  : MSI registers



- device_type: must be "pci"

- apio-wins : number of requested apio outbound windows

		default 2 outbound windows are configured -

		1. Config window

		2. Memory window

- ppio-wins : number of requested ppio inbound windows

		default 1 inbound memory window is configured.

- bus-range: PCI bus numbers covered

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: specifies the number of cells needed to encode an

	interrupt source. The value must be 1.

- interrupts: The interrupt line of the PCIe controller

		last cell of this field is set to 4 to

		denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.

- interrupt-map-mask,

	interrupt-map: standard PCI properties to define the mapping of the

	PCI interface to interrupt numbers.

- ranges: ranges for the PCI memory regions (I/O space region is not

	supported by hardware)

	Please refer to the standard PCI bus binding document for a more

	detailed explanation





Example:

++++++++

	pcie0: pcie@a0000000 {

		#address-cells = <3>;

		#size-cells = <2>;

		compatible = "mbvl,gpex40-pcie";

		reg =	<0xa0000000 0x00001000>,

			<0xb0000000 0x00010000>,

			<0xff000000 0x00200000>,

			<0xb0010000 0x00001000>;

		reg-names =	"config_axi_slave",

				"csr_axi_slave",

				"gpio_slave",

				"apb_csr";

		device_type = "pci";

		apio-wins = <2>;

		ppio-wins = <1>;

		bus-range = <0x00000000 0x000000ff>;

		interrupt-controller;

		interrupt-parent = <&gic>;

		#interrupt-cells = <1>;

		interrupts = < 0 89 4 >;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 0 &pci_express 0>,

				<0 0 0 1 &pci_express 1>,

				<0 0 0 2 &pci_express 2>,

				<0 0 0 3 &pci_express 3>;

		ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;



	};

Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml

+6 −3
Original line number Diff line number Diff line
@@ -57,9 +57,10 @@ properties: 


  interrupts:

    minItems: 8

    maxItems: 8

    maxItems: 9



  interrupt-names:

    minItems: 8

    items:

      - const: msi0

      - const: msi1
@@ -69,6 +70,7 @@ properties: 
      - const: msi5

      - const: msi6

      - const: msi7

      - const: global



  resets:

    minItems: 1
@@ -139,9 +141,10 @@ examples: 
                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "msi0", "msi1", "msi2", "msi3",

                              "msi4", "msi5", "msi6", "msi7";

                              "msi4", "msi5", "msi6", "msi7", "global";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0x7>;

            interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

Documentation/devicetree/bindings/pci/qcom,pcie.yaml

+4 −0
Original line number Diff line number Diff line
@@ -31,6 +31,10 @@ properties: 
          - qcom,pcie-qcs404

          - qcom,pcie-sdm845

          - qcom,pcie-sdx55

      - items:

          - enum:

              - qcom,pcie-ipq5424

          - const: qcom,pcie-ipq9574

      - items:

          - const: qcom,pcie-msm8998

          - const: qcom,pcie-msm8996