Commit 1536dc8e authored by Beniamin Sandu's avatar Beniamin Sandu Committed by Dinh Nguyen
Browse files

arm64: dts: socfpga: stratix10: add L2 cache info 



This removes cacheinfo warnings at boot, e.g.:
cacheinfo: Unable to detect cache hierarchy for CPU 0

Signed-off-by: default avatarBeniamin Sandu <beniaminsandu@gmail.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 32cdf4c7

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ cpu0: cpu@0 { 
			compatible = "arm,cortex-a53";

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&l2_shared>;

			reg = <0x0>;

		};
@@ -41,6 +42,7 @@ cpu1: cpu@1 { 
			compatible = "arm,cortex-a53";

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&l2_shared>;

			reg = <0x1>;

		};
@@ -48,6 +50,7 @@ cpu2: cpu@2 { 
			compatible = "arm,cortex-a53";

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&l2_shared>;

			reg = <0x2>;

		};
@@ -55,8 +58,15 @@ cpu3: cpu@3 { 
			compatible = "arm,cortex-a53";

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&l2_shared>;

			reg = <0x3>;

		};



		l2_shared: cache {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};



	firmware {