Commit 16438b65 authored by Ilkka Koskinen's avatar Ilkka Koskinen Committed by Arnaldo Carvalho de Melo
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perf vendor events arm64 AmpereOneX: Add core PMU events and metrics 



Add JSON files for AmpereOneX core PMU events and metrics.

Reviewed-by: default avatarIan Rogers <irogers@google.com>
Signed-off-by: default avatarIlkka Koskinen <ilkka@os.amperecomputing.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20231201021550.1109196-4-ilkka@os.amperecomputing.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 10a149e4

tools/perf/pmu-events/arch/arm64/ampere/ampereonex/branch.json

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[

    {

        "ArchStdEvent": "BR_IMMED_SPEC"

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    },

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    },

    {

        "PublicDescription": "Instruction architecturally executed, branch not taken",

        "EventCode": "0x8107",

        "EventName": "BR_SKIP_RETIRED",

        "BriefDescription": "Instruction architecturally executed, branch not taken"

    },

    {

        "PublicDescription": "Instruction architecturally executed, immediate branch taken",

        "EventCode": "0x8108",

        "EventName": "BR_IMMED_TAKEN_RETIRED",

        "BriefDescription": "Instruction architecturally executed, immediate branch taken"

    },

    {

        "PublicDescription": "Instruction architecturally executed, indirect branch excluding return retired",

        "EventCode": "0x810c",

        "EventName": "BR_INDNR_TAKEN_RETIRED",

        "BriefDescription": "Instruction architecturally executed, indirect branch excluding return retired"

    },

    {

        "PublicDescription": "Instruction architecturally executed, predicted immediate branch",

        "EventCode": "0x8110",

        "EventName": "BR_IMMED_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, predicted immediate branch"

    },

    {

        "PublicDescription": "Instruction architecturally executed, mispredicted immediate branch",

        "EventCode": "0x8111",

        "EventName": "BR_IMMED_MIS_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, mispredicted immediate branch"

    },

    {

        "PublicDescription": "Instruction architecturally executed, predicted indirect branch",

        "EventCode": "0x8112",

        "EventName": "BR_IND_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, predicted indirect branch"

    },

    {

        "PublicDescription": "Instruction architecturally executed, mispredicted indirect branch",

        "EventCode": "0x8113",

        "EventName": "BR_IND_MIS_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, mispredicted indirect branch"

    },

    {

        "PublicDescription": "Instruction architecturally executed, predicted procedure return",

        "EventCode": "0x8114",

        "EventName": "BR_RETURN_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, predicted procedure return"

    },

    {

        "PublicDescription": "Instruction architecturally executed, mispredicted procedure return",

        "EventCode": "0x8115",

        "EventName": "BR_RETURN_MIS_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, mispredicted procedure return"

    },

    {

        "PublicDescription": "Instruction architecturally executed, predicted indirect branch excluding return",

        "EventCode": "0x8116",

        "EventName": "BR_INDNR_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, predicted indirect branch excluding return"

    },

    {

        "PublicDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return",

        "EventCode": "0x8117",

        "EventName": "BR_INDNR_MIS_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return"

    },

    {

        "PublicDescription": "Instruction architecturally executed, predicted branch, taken",

        "EventCode": "0x8118",

        "EventName": "BR_TAKEN_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, predicted branch, taken"

    },

    {

        "PublicDescription": "Instruction architecturally executed, mispredicted branch, taken",

        "EventCode": "0x8119",

        "EventName": "BR_TAKEN_MIS_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, mispredicted branch, taken"

    },

    {

        "PublicDescription": "Instruction architecturally executed, predicted branch, not taken",

        "EventCode": "0x811a",

        "EventName": "BR_SKIP_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, predicted branch, not taken"

    },

    {

        "PublicDescription": "Instruction architecturally executed, mispredicted branch, not taken",

        "EventCode": "0x811b",

        "EventName": "BR_SKIP_MIS_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, mispredicted branch, not taken"

    },

    {

        "PublicDescription": "Instruction architecturally executed, predicted branch",

        "EventCode": "0x811c",

        "EventName": "BR_PRED_RETIRED",

        "BriefDescription": "Instruction architecturally executed, predicted branch"

    },

    {

        "PublicDescription": "Instruction architecturally executed, indirect branch",

        "EventCode": "0x811d",

        "EventName": "BR_IND_RETIRED",

        "BriefDescription": "Instruction architecturally executed, indirect branch"

    },

    {

        "PublicDescription": "Branch Record captured.",

        "EventCode": "0x811f",

        "EventName": "BRB_FILTRATE",

        "BriefDescription": "Branch Record captured."

    }

]

tools/perf/pmu-events/arch/arm64/ampere/ampereonex/bus.json

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[

    {

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

    },

    {

        "ArchStdEvent": "CNT_CYCLES"

    }

]

tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json

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[

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L1D_TLB"

    },

    {

        "ArchStdEvent": "L1I_TLB"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2D_TLB"

    },

    {

        "ArchStdEvent": "L2I_TLB"

    },

    {

        "ArchStdEvent": "DTLB_WALK"

    },

    {

        "ArchStdEvent": "ITLB_WALK"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_LMISS_RD"

    },

    {

        "ArchStdEvent": "L1I_CACHE_LMISS"

    },

    {

        "ArchStdEvent": "L2D_CACHE_LMISS_RD"

    },

    {

        "PublicDescription": "Level 1 data or unified cache demand access",

        "EventCode": "0x8140",

        "EventName": "L1D_CACHE_RW",

        "BriefDescription": "Level 1 data or unified cache demand access"

    },

    {

        "PublicDescription": "Level 1 data or unified cache preload or prefetch",

        "EventCode": "0x8142",

        "EventName": "L1D_CACHE_PRFM",

        "BriefDescription": "Level 1 data or unified cache preload or prefetch"

    },

    {

        "PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",

        "EventCode": "0x8146",

        "EventName": "L1D_CACHE_REFILL_PRFM",

        "BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"

    },

    {

        "ArchStdEvent": "L1D_TLB_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_WR"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_TLB_RD"

    },

    {

        "ArchStdEvent": "L2D_TLB_WR"

    },

    {

        "PublicDescription": "L1D TLB miss",

        "EventCode": "0xD600",

        "EventName": "L1D_TLB_MISS",

        "BriefDescription": "L1D TLB miss"

    },

    {

        "PublicDescription": "Level 1 prefetcher, load prefetch requests generated",

        "EventCode": "0xd606",

        "EventName": "L1_PREFETCH_LD_GEN",

        "BriefDescription": "Level 1 prefetcher, load prefetch requests generated"

    },

    {

        "PublicDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache",

        "EventCode": "0xd607",

        "EventName": "L1_PREFETCH_LD_FILL",

        "BriefDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache"

    },

    {

        "PublicDescription": "Level 1 prefetcher, load prefetch to level 2 generated",

        "EventCode": "0xd608",

        "EventName": "L1_PREFETCH_L2_REQ",

        "BriefDescription": "Level 1 prefetcher, load prefetch to level 2 generated"

    },

    {

        "PublicDescription": "L1 prefetcher, distance was reset",

        "EventCode": "0xd609",

        "EventName": "L1_PREFETCH_DIST_RST",

        "BriefDescription": "L1 prefetcher, distance was reset"

    },

    {

        "PublicDescription": "L1 prefetcher, distance was increased",

        "EventCode": "0xd60a",

        "EventName": "L1_PREFETCH_DIST_INC",

        "BriefDescription": "L1 prefetcher, distance was increased"

    },

    {

        "PublicDescription": "Level 1 prefetcher, table entry is trained",

        "EventCode": "0xd60b",

        "EventName": "L1_PREFETCH_ENTRY_TRAINED",

        "BriefDescription": "Level 1 prefetcher, table entry is trained"

    },

    {

        "PublicDescription": "L1 data cache refill - Read or Write",

        "EventCode": "0xd60e",

        "EventName": "L1D_CACHE_REFILL_RW",

        "BriefDescription": "L1 data cache refill - Read or Write"

    },

    {

        "PublicDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills",

        "EventCode": "0xD701",

        "EventName": "L2C_INST_REFILL",

        "BriefDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills"

    },

    {

        "PublicDescription": "Level 2 cache refill from data-side miss, including DMMU refills",

        "EventCode": "0xD702",

        "EventName": "L2C_DATA_REFILL",

        "BriefDescription": "Level 2 cache refill from data-side miss, including DMMU refills"

    },

    {

        "PublicDescription": "Level 2 cache prefetcher, load prefetch requests generated",

        "EventCode": "0xD703",

        "EventName": "L2_PREFETCH_REQ",

        "BriefDescription": "Level 2 cache prefetcher, load prefetch requests generated"

    }

]

tools/perf/pmu-events/arch/arm64/ampere/ampereonex/core-imp-def.json

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File added.

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tools/perf/pmu-events/arch/arm64/ampere/ampereonex/exception.json

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[

    {

        "ArchStdEvent": "EXC_UNDEF"

    },

    {

        "ArchStdEvent": "EXC_SVC"

    },

    {

        "ArchStdEvent": "EXC_PABORT"

    },

    {

        "ArchStdEvent": "EXC_DABORT"

    },

    {

        "ArchStdEvent": "EXC_IRQ"

    },

    {

        "ArchStdEvent": "EXC_FIQ"

    },

    {

        "ArchStdEvent": "EXC_HVC"

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER"

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ"

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ"

    },

    {

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "EXC_RETURN"

    },

    {

        "ArchStdEvent": "EXC_SMC"

    }

]