Commit 167ec660 authored by Frank Li's avatar Frank Li Committed by Vinod Koul
Browse files

dt-bindings: dma: fsl-edma: allow 'power-domains' property 



Allow 'power-domains' property because i.MX8DXL i.MX8QM and i.MX8QXP need
it. EDMA supports each power-domain for each dma channel. So minItems and
maxItems align 'dma-channels'.

Change fsl,imx93-edma3 example to fsl,imx8qm-edma to reflect this variants.

Fixed below DTB_CHECK warning:
  dma-controller@599f0000: Unevaluated properties are not allowed ('power-domains' was unexpected)

Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240417152457.361340-2-Frank.Li@nxp.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9c21bbfa

Documentation/devicetree/bindings/dma/fsl,edma.yaml

+42 −38
Original line number Diff line number Diff line
@@ -70,6 +70,13 @@ properties: 
    minItems: 1

    maxItems: 33



  power-domains:

    description:

      The number of power domains matches the number of channels, arranged

      in ascending order according to their associated DMA channels.

    minItems: 1

    maxItems: 64



  big-endian:

    description: |

      If present registers and hardware scatter/gather descriptors of the
@@ -200,6 +207,20 @@ allOf: 
      required:

        - clocks



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qm-adma

              - fsl,imx8qm-edma

    then:

      required:

        - power-domains

    else:

      properties:

        power-domains: false



unevaluatedProperties: false



examples:
@@ -255,44 +276,27 @@ examples: 


  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/imx93-clock.h>

    #include <dt-bindings/firmware/imx/rsrc.h>



    dma-controller@44000000 {

      compatible = "fsl,imx93-edma3";

      reg = <0x44000000 0x200000>;

    dma-controller@5a9f0000 {

      compatible = "fsl,imx8qm-edma";

      reg = <0x5a9f0000 0x90000>;

      #dma-cells = <3>;

      dma-channels = <31>;

      interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clk IMX93_CLK_EDMA1_GATE>;

        clock-names = "dma";

      dma-channels = <8>;

      interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;

      power-domains = <&pd IMX_SC_R_DMA_3_CH0>,

                      <&pd IMX_SC_R_DMA_3_CH1>,

                      <&pd IMX_SC_R_DMA_3_CH2>,

                      <&pd IMX_SC_R_DMA_3_CH3>,

                      <&pd IMX_SC_R_DMA_3_CH4>,

                      <&pd IMX_SC_R_DMA_3_CH5>,

                      <&pd IMX_SC_R_DMA_3_CH6>,

                      <&pd IMX_SC_R_DMA_3_CH7>;

    };