Commit 1683a3c7 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sc: change labels to lower-case 



DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-6-0505bc7d2c56@linaro.org


[bjorn: Update sm7325 references to match the updated case]
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 183c7c04

arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
/ {

	cpus {

		domain_idle_states: domain-idle-states {

			CLUSTER_SLEEP_0: cluster-sleep-0 {

			cluster_sleep_0: cluster-sleep-0 {

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x40003444>;

				entry-latency-us = <2752>;
@@ -52,8 +52,8 @@ venus_mem: memory@8b200000 { 
	};

};



&CLUSTER_PD {

	domain-idle-states = <&CLUSTER_SLEEP_0>;

&cluster_pd {

	domain-idle-states = <&cluster_sleep_0>;

};



&gpu {

arch/arm64/boot/dts/qcom/sc7280.dtsi

+187 −187

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm64/boot/dts/qcom/sc8180x.dtsi

+82 −82
Original line number Diff line number Diff line
@@ -42,28 +42,28 @@ cpus { 
		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x0>;

			enable-method = "psci";

			capacity-dmips-mhz = <602>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&l2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD0>;

			power-domains = <&cpu_pd0>;

			power-domain-names = "psci";

			#cooling-cells = <2>;

			clocks = <&cpufreq_hw 0>;



			L2_0: l2-cache {

			l2_0: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				L3_0: l3-cache {

				next-level-cache = <&l3_0>;

				l3_0: l3-cache {

					compatible = "cache";

					cache-level = <3>;

					cache-unified;
@@ -71,207 +71,207 @@ L3_0: l3-cache { 
			};

		};



		CPU1: cpu@100 {

		cpu1: cpu@100 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x100>;

			enable-method = "psci";

			capacity-dmips-mhz = <602>;

			next-level-cache = <&L2_100>;

			next-level-cache = <&l2_100>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD1>;

			power-domains = <&cpu_pd1>;

			power-domain-names = "psci";

			#cooling-cells = <2>;

			clocks = <&cpufreq_hw 0>;



			L2_100: l2-cache {

			l2_100: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};



		};



		CPU2: cpu@200 {

		cpu2: cpu@200 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x200>;

			enable-method = "psci";

			capacity-dmips-mhz = <602>;

			next-level-cache = <&L2_200>;

			next-level-cache = <&l2_200>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD2>;

			power-domains = <&cpu_pd2>;

			power-domain-names = "psci";

			#cooling-cells = <2>;

			clocks = <&cpufreq_hw 0>;



			L2_200: l2-cache {

			l2_200: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU3: cpu@300 {

		cpu3: cpu@300 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x300>;

			enable-method = "psci";

			capacity-dmips-mhz = <602>;

			next-level-cache = <&L2_300>;

			next-level-cache = <&l2_300>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD3>;

			power-domains = <&cpu_pd3>;

			power-domain-names = "psci";

			#cooling-cells = <2>;

			clocks = <&cpufreq_hw 0>;



			L2_300: l2-cache {

			l2_300: l2-cache {

				compatible = "cache";

				cache-unified;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU4: cpu@400 {

		cpu4: cpu@400 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x400>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&L2_400>;

			next-level-cache = <&l2_400>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			operating-points-v2 = <&cpu4_opp_table>;

			interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD4>;

			power-domains = <&cpu_pd4>;

			power-domain-names = "psci";

			#cooling-cells = <2>;

			clocks = <&cpufreq_hw 1>;



			L2_400: l2-cache {

			l2_400: l2-cache {

				compatible = "cache";

				cache-unified;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU5: cpu@500 {

		cpu5: cpu@500 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x500>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&L2_500>;

			next-level-cache = <&l2_500>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			operating-points-v2 = <&cpu4_opp_table>;

			interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD5>;

			power-domains = <&cpu_pd5>;

			power-domain-names = "psci";

			#cooling-cells = <2>;

			clocks = <&cpufreq_hw 1>;



			L2_500: l2-cache {

			l2_500: l2-cache {

				compatible = "cache";

				cache-unified;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU6: cpu@600 {

		cpu6: cpu@600 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x600>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&L2_600>;

			next-level-cache = <&l2_600>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			operating-points-v2 = <&cpu4_opp_table>;

			interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD6>;

			power-domains = <&cpu_pd6>;

			power-domain-names = "psci";

			#cooling-cells = <2>;

			clocks = <&cpufreq_hw 1>;



			L2_600: l2-cache {

			l2_600: l2-cache {

				compatible = "cache";

				cache-unified;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU7: cpu@700 {

		cpu7: cpu@700 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x700>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			next-level-cache = <&L2_700>;

			next-level-cache = <&l2_700>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			operating-points-v2 = <&cpu4_opp_table>;

			interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD7>;

			power-domains = <&cpu_pd7>;

			power-domain-names = "psci";

			#cooling-cells = <2>;

			clocks = <&cpufreq_hw 1>;



			L2_700: l2-cache {

			l2_700: l2-cache {

				compatible = "cache";

				cache-unified;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

					cpu = <&cpu0>;

				};



				core1 {

					cpu = <&CPU1>;

					cpu = <&cpu1>;

				};



				core2 {

					cpu = <&CPU2>;

					cpu = <&cpu2>;

				};



				core3 {

					cpu = <&CPU3>;

					cpu = <&cpu3>;

				};



				core4 {

					cpu = <&CPU4>;

					cpu = <&cpu4>;

				};



				core5 {

					cpu = <&CPU5>;

					cpu = <&cpu5>;

				};



				core6 {

					cpu = <&CPU6>;

					cpu = <&cpu6>;

				};



				core7 {

					cpu = <&CPU7>;

					cpu = <&cpu7>;

				};

			};

		};
@@ -279,7 +279,7 @@ core7 { 
		idle-states {

			entry-method = "psci";



			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {

			little_cpu_sleep_0: cpu-sleep-0-0 {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x40000004>;

				entry-latency-us = <355>;
@@ -288,7 +288,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 
				local-timer-stop;

			};



			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {

			big_cpu_sleep_0: cpu-sleep-1-0 {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x40000004>;

				entry-latency-us = <2411>;
@@ -299,7 +299,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 
		};



		domain-idle-states {

			CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {

			cluster_sleep_apss_off: cluster-sleep-0 {

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x41000044>;

				entry-latency-us = <3300>;
@@ -307,7 +307,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 
				min-residency-us = <6000>;

			};



			CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {

			cluster_sleep_aoss_sleep: cluster-sleep-1 {

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x4100a344>;

				entry-latency-us = <3263>;
@@ -541,57 +541,57 @@ psci { 
		compatible = "arm,psci-1.0";

		method = "smc";



		CPU_PD0: power-domain-cpu0 {

		cpu_pd0: power-domain-cpu0 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD1: power-domain-cpu1 {

		cpu_pd1: power-domain-cpu1 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD2: power-domain-cpu2 {

		cpu_pd2: power-domain-cpu2 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD3: power-domain-cpu3 {

		cpu_pd3: power-domain-cpu3 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD4: power-domain-cpu4 {

		cpu_pd4: power-domain-cpu4 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&big_cpu_sleep_0>;

		};



		CPU_PD5: power-domain-cpu5 {

		cpu_pd5: power-domain-cpu5 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&big_cpu_sleep_0>;

		};



		CPU_PD6: power-domain-cpu6 {

		cpu_pd6: power-domain-cpu6 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&big_cpu_sleep_0>;

		};



		CPU_PD7: power-domain-cpu7 {

		cpu_pd7: power-domain-cpu7 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&big_cpu_sleep_0>;

		};



		CLUSTER_PD: power-domain-cpu-cluster0 {

		cluster_pd: power-domain-cpu-cluster0 {

			#power-domain-cells = <0>;

			domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;

			domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;

		};

	};
@@ -3790,7 +3790,7 @@ apps_rsc: rsc@18200000 { 
					  <WAKE_TCS    1>,

					  <CONTROL_TCS 0>;

			label = "apps_rsc";

			power-domains = <&CLUSTER_PD>;

			power-domains = <&cluster_pd>;



			apps_bcm_voter: bcm-voter {

				compatible = "qcom,bcm-voter";
@@ -3868,7 +3868,7 @@ lmh@18350800 { 
			compatible = "qcom,sc8180x-lmh";

			reg = <0 0x18350800 0 0x400>;

			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

			cpus = <&CPU4>;

			cpus = <&cpu4>;

			qcom,lmh-temp-arm-millicelsius = <65000>;

			qcom,lmh-temp-low-millicelsius = <94500>;

			qcom,lmh-temp-high-millicelsius = <95000>;
@@ -3880,7 +3880,7 @@ lmh@18358800 { 
			compatible = "qcom,sc8180x-lmh";

			reg = <0 0x18358800 0 0x400>;

			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

			cpus = <&CPU0>;

			cpus = <&cpu0>;

			qcom,lmh-temp-arm-millicelsius = <65000>;

			qcom,lmh-temp-low-millicelsius = <94500>;

			qcom,lmh-temp-high-millicelsius = <95000>;

arch/arm64/boot/dts/qcom/sm7325.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -7,11 +7,11 @@ 
#include "sc7280.dtsi"



/* SM7325 uses Kryo 670 */

&CPU0 { compatible = "qcom,kryo670"; };

&CPU1 { compatible = "qcom,kryo670"; };

&CPU2 { compatible = "qcom,kryo670"; };

&CPU3 { compatible = "qcom,kryo670"; };

&CPU4 { compatible = "qcom,kryo670"; };

&CPU5 { compatible = "qcom,kryo670"; };

&CPU6 { compatible = "qcom,kryo670"; };

&CPU7 { compatible = "qcom,kryo670"; };
 
&cpu0 { compatible = "qcom,kryo670"; };

&cpu1 { compatible = "qcom,kryo670"; };

&cpu2 { compatible = "qcom,kryo670"; };

&cpu3 { compatible = "qcom,kryo670"; };

&cpu4 { compatible = "qcom,kryo670"; };

&cpu5 { compatible = "qcom,kryo670"; };

&cpu6 { compatible = "qcom,kryo670"; };

&cpu7 { compatible = "qcom,kryo670"; };