Commit 171596bf authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xe3lpd: Add new display power wells 



Xe3's power well handling is similar to previous platforms, but there
are a few changes that need to be handled to ensure optimal power
management:
 - PGB now only depends on PG1, not PG2
 - Transcoder B is now in PG1 (was previously in PGB)
 - Transcoders C & D are now in PG2 (were previously in PGC/PGD)
 - DC states now require PG2 to be off (whereas on Xe2 it could remain
   on as a dependency of PGB, although the features inside of it could
   not be used).

Bspec: 72519, 68851
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: default avatarLuca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241010224311.50133-4-matthew.s.atwood@intel.com
parent a6e40f6d

drivers/gpu/drm/i915/display/intel_display_power_map.c

+133 −1
Original line number Diff line number Diff line
@@ -1586,6 +1586,136 @@ static const struct i915_power_well_desc_list xe2lpd_power_wells[] = { 
	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),

};



/*

 * Xe3 changes the power well hierarchy slightly from Xe_LPD+; PGB now

 * depends on PG1 instead of PG2:

 *

 *       PG0

 *        |

 *     --PG1--

 *    /   |   \

 *  PGA  PGB  PG2

 *           /   \

 *         PGC   PGD

 */



#define XE3LPD_PW_C_POWER_DOMAINS \

	POWER_DOMAIN_PIPE_C, \

	POWER_DOMAIN_PIPE_PANEL_FITTER_C



#define XE3LPD_PW_D_POWER_DOMAINS \

	POWER_DOMAIN_PIPE_D, \

	POWER_DOMAIN_PIPE_PANEL_FITTER_D



#define XE3LPD_PW_2_POWER_DOMAINS \

	XE3LPD_PW_C_POWER_DOMAINS, \

	XE3LPD_PW_D_POWER_DOMAINS, \

	POWER_DOMAIN_TRANSCODER_C, \

	POWER_DOMAIN_TRANSCODER_D, \

	POWER_DOMAIN_VGA, \

	POWER_DOMAIN_PORT_DDI_LANES_TC1, \

	POWER_DOMAIN_PORT_DDI_LANES_TC2, \

	POWER_DOMAIN_PORT_DDI_LANES_TC3, \

	POWER_DOMAIN_PORT_DDI_LANES_TC4



I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_2,

		     XE3LPD_PW_2_POWER_DOMAINS,

		     POWER_DOMAIN_INIT);



I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_b,

		     POWER_DOMAIN_PIPE_B,

		     POWER_DOMAIN_PIPE_PANEL_FITTER_B,

		     POWER_DOMAIN_INIT);



I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_c,

		     XE3LPD_PW_C_POWER_DOMAINS,

		     POWER_DOMAIN_INIT);



I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_d,

		     XE3LPD_PW_D_POWER_DOMAINS,

		     POWER_DOMAIN_INIT);



static const struct i915_power_well_desc xe3lpd_power_wells_main[] = {

	{

		.instances = &I915_PW_INSTANCES(

			I915_PW("PW_2", &xe3lpd_pwdoms_pw_2,

				.hsw.idx = ICL_PW_CTL_IDX_PW_2,

				.id = SKL_DISP_PW_2),

		),

		.ops = &hsw_power_well_ops,

		.has_vga = true,

		.has_fuses = true,

	}, {

		.instances = &I915_PW_INSTANCES(

			I915_PW("PW_A", &xelpd_pwdoms_pw_a,

				.hsw.idx = XELPD_PW_CTL_IDX_PW_A),

		),

		.ops = &hsw_power_well_ops,

		.irq_pipe_mask = BIT(PIPE_A),

		.has_fuses = true,

	}, {

		.instances = &I915_PW_INSTANCES(

			I915_PW("PW_B", &xe3lpd_pwdoms_pw_b,

				.hsw.idx = XELPD_PW_CTL_IDX_PW_B),

		),

		.ops = &hsw_power_well_ops,

		.irq_pipe_mask = BIT(PIPE_B),

		.has_fuses = true,

	}, {

		.instances = &I915_PW_INSTANCES(

			I915_PW("PW_C", &xe3lpd_pwdoms_pw_c,

				.hsw.idx = XELPD_PW_CTL_IDX_PW_C),

		),

		.ops = &hsw_power_well_ops,

		.irq_pipe_mask = BIT(PIPE_C),

		.has_fuses = true,

	}, {

		.instances = &I915_PW_INSTANCES(

			I915_PW("PW_D", &xe3lpd_pwdoms_pw_d,

				.hsw.idx = XELPD_PW_CTL_IDX_PW_D),

		),

		.ops = &hsw_power_well_ops,

		.irq_pipe_mask = BIT(PIPE_D),

		.has_fuses = true,

	}, {

		.instances = &I915_PW_INSTANCES(

			I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),

			I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),

			I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),

			I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),

			I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3),

			I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4),

		),

		.ops = &xelpdp_aux_power_well_ops,

	},

};



I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_dc_off,

	POWER_DOMAIN_DC_OFF,

	XE3LPD_PW_2_POWER_DOMAINS,

	XE3LPD_PW_C_POWER_DOMAINS,

	XE3LPD_PW_D_POWER_DOMAINS,

	POWER_DOMAIN_AUDIO_MMIO,

	POWER_DOMAIN_INIT);



static const struct i915_power_well_desc xe3lpd_power_wells_dcoff[] = {

	{

		.instances = &I915_PW_INSTANCES(

			I915_PW("DC_off", &xe3lpd_pwdoms_dc_off,

				.id = SKL_DISP_DC_OFF),

		),

		.ops = &gen9_dc_off_power_well_ops,

	},

};



static const struct i915_power_well_desc_list xe3lpd_power_wells[] = {

	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),

	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),

	I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff),

	I915_PW_DESCRIPTORS(xe3lpd_power_wells_main),

	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),

};



static void init_power_well_domains(const struct i915_power_well_instance *inst,

				    struct i915_power_well *power_well)

{
@@ -1693,7 +1823,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains) 
		return 0;

	}



	if (DISPLAY_VER(i915) >= 20)

	if (DISPLAY_VER(i915) >= 30)

		return set_power_wells(power_domains, xe3lpd_power_wells);

	else if (DISPLAY_VER(i915) >= 20)

		return set_power_wells(power_domains, xe2lpd_power_wells);

	else if (DISPLAY_VER(i915) >= 14)

		return set_power_wells(power_domains, xelpdp_power_wells);