Commit 1884f54e authored by Wolfram Sang's avatar Wolfram Sang
Browse files

Merge tag 'i2c-host-6.18-pt2' of... 

Merge tag 'i2c-host-6.18-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow

i2c-host for v6.18, part 2

rtl9300 updates:
 - general cleanups
 - implemented block read/write support
 - added RTL9310 support
parents cbf33b8e 1e33137d

Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml

+40 −5
Original line number Diff line number Diff line
@@ -10,9 +10,11 @@ maintainers: 
  - Chris Packham <chris.packham@alliedtelesis.co.nz>



description:

  The RTL9300 SoC has two I2C controllers. Each of these has an SCL line (which

  RTL9300 SoCs have two I2C controllers. Each of these has an SCL line (which

  if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be

  assigned to either I2C controller.

  RTL9310 SoCs have equal capabilities but support 12 common SDA lines which

  can be assigned to either I2C controller.



properties:

  compatible:
@@ -23,11 +25,19 @@ properties: 
              - realtek,rtl9302c-i2c

              - realtek,rtl9303-i2c

          - const: realtek,rtl9301-i2c

      - const: realtek,rtl9301-i2c

      - items:

          - enum:

              - realtek,rtl9311-i2c

              - realtek,rtl9312-i2c

              - realtek,rtl9313-i2c

          - const: realtek,rtl9310-i2c

      - enum:

          - realtek,rtl9301-i2c

          - realtek,rtl9310-i2c



  reg:

    items:

      - description: Register offset and size this I2C controller.

      - description: Register offset and size of this I2C controller.



  "#address-cells":

    const: 1
@@ -35,19 +45,44 @@ properties: 
  "#size-cells":

    const: 0



  realtek,scl:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      The SCL line number of this I2C controller.

    enum: [ 0, 1 ]



patternProperties:

  '^i2c@[0-7]$':

  '^i2c@[0-9ab]$':

    $ref: /schemas/i2c/i2c-controller.yaml

    unevaluatedProperties: false



    properties:

      reg:

        description: The SDA pin associated with the I2C bus.

        description: The SDA line number associated with the I2C bus.

        maxItems: 1



    required:

      - reg





allOf:

  - if:

      properties:

        compatible:

          contains:

            const: realtek,rtl9310-i2c

    then:

      required:

        - realtek,scl

  - if:

      properties:

        compatible:

          contains:

            const: realtek,rtl9301-i2c

    then:

      patternProperties:

        '^i2c@[89ab]$': false



required:

  - compatible

  - reg

drivers/i2c/busses/i2c-rtl9300.c

+289 −170
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <linux/mutex.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <linux/unaligned.h>



enum rtl9300_bus_freq {

	RTL9300_I2C_STD_FREQ,
@@ -20,103 +21,143 @@ struct rtl9300_i2c_chan { 
	struct i2c_adapter adap;

	struct rtl9300_i2c *i2c;

	enum rtl9300_bus_freq bus_freq;

	u8 sda_pin;

	u8 sda_num;

};



enum rtl9300_i2c_reg_scope {

	REG_SCOPE_GLOBAL,

	REG_SCOPE_MASTER,

};



struct rtl9300_i2c_reg_field {

	struct reg_field field;

	enum rtl9300_i2c_reg_scope scope;

};



enum rtl9300_i2c_reg_fields {

	F_DATA_WIDTH = 0,

	F_DEV_ADDR,

	F_I2C_FAIL,

	F_I2C_TRIG,

	F_MEM_ADDR,

	F_MEM_ADDR_WIDTH,

	F_RD_MODE,

	F_RWOP,

	F_SCL_FREQ,

	F_SCL_SEL,

	F_SDA_OUT_SEL,

	F_SDA_SEL,



	/* keep last */

	F_NUM_FIELDS

};



struct rtl9300_i2c_drv_data {

	struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS];

	int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl);

	u32 data_reg;

	u8 max_nchan;

};



#define RTL9300_I2C_MUX_NCHAN	8

#define RTL9310_I2C_MUX_NCHAN	12



struct rtl9300_i2c {

	struct regmap *regmap;

	struct device *dev;

	struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN];

	struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN];

	struct regmap_field *fields[F_NUM_FIELDS];

	u32 reg_base;

	u8 sda_pin;

	u32 data_reg;

	u8 scl_num;

	u8 sda_num;

	struct mutex lock;

};



DEFINE_GUARD(rtl9300_i2c, struct rtl9300_i2c *, mutex_lock(&_T->lock), mutex_unlock(&_T->lock))



enum rtl9300_i2c_xfer_type {

	RTL9300_I2C_XFER_BYTE,

	RTL9300_I2C_XFER_WORD,

	RTL9300_I2C_XFER_BLOCK,

};



struct rtl9300_i2c_xfer {

	enum rtl9300_i2c_xfer_type type;

	u16 dev_addr;

	u8 reg_addr;

	u8 reg_addr_len;

	u8 *data;

	u8 data_len;

	bool write;

};



#define RTL9300_I2C_MST_CTRL1				0x0

#define  RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS		8

#define  RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK		GENMASK(31, 8)

#define  RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS		4

#define  RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK		GENMASK(6, 4)

#define  RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL		BIT(3)

#define  RTL9300_I2C_MST_CTRL1_RWOP			BIT(2)

#define  RTL9300_I2C_MST_CTRL1_I2C_FAIL			BIT(1)

#define  RTL9300_I2C_MST_CTRL1_I2C_TRIG			BIT(0)

#define RTL9300_I2C_MST_CTRL2				0x4

#define  RTL9300_I2C_MST_CTRL2_RD_MODE			BIT(15)

#define  RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS		8

#define  RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK		GENMASK(14, 8)

#define  RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS		4

#define  RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK		GENMASK(7, 4)

#define  RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS	2

#define  RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK	GENMASK(3, 2)

#define  RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS		0

#define  RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK		GENMASK(1, 0)

#define RTL9300_I2C_MST_DATA_WORD0			0x8

#define RTL9300_I2C_MST_DATA_WORD1			0xc

#define RTL9300_I2C_MST_DATA_WORD2			0x10

#define RTL9300_I2C_MST_DATA_WORD3			0x14



#define RTL9300_I2C_MST_GLB_CTRL			0x384



#define RTL9310_I2C_MST_IF_CTRL				0x1004

#define RTL9310_I2C_MST_IF_SEL				0x1008

#define RTL9310_I2C_MST_CTRL				0x0

#define RTL9310_I2C_MST_MEMADDR_CTRL			0x4

#define RTL9310_I2C_MST_DATA_CTRL			0x8



static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)

{

	u32 val, mask;

	int ret;



	val = len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS;

	mask = RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK;



	ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);

	ret = regmap_field_write(i2c->fields[F_MEM_ADDR_WIDTH], len);

	if (ret)

		return ret;



	val = reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS;

	mask = RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK;



	return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);

	return regmap_field_write(i2c->fields[F_MEM_ADDR], reg);

}



static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin)

static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)

{

	int ret;

	u32 val, mask;



	ret = regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda_pin), BIT(sda_pin));

	if (ret)

		return ret;



	val = (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) |

		RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;

	mask = RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;

	return regmap_field_write(i2c->fields[F_SCL_SEL], 1);

}



	return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);

static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)

{

	return regmap_field_update_bits(i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl));

}



static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan,

				   u16 addr, u16 len)

static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan)

{

	u32 val, mask;

	struct rtl9300_i2c_drv_data *drv_data;

	int ret;



	if (len < 1 || len > 16)

		return -EINVAL;

	if (i2c->sda_num == chan->sda_num)

		return 0;



	val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS;

	mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK;

	ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq);

	if (ret)

		return ret;



	val |= addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS;

	mask |= RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK;

	drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);

	ret = drv_data->select_scl(i2c, i2c->scl_num);

	if (ret)

		return ret;



	val |= ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS;

	mask |= RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK;

	ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(chan->sda_num),

				       BIT(chan->sda_num));

	if (ret)

		return ret;



	mask |= RTL9300_I2C_MST_CTRL2_RD_MODE;

	ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], chan->sda_num);

	if (ret)

		return ret;



	return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);

	i2c->sda_num = chan->sda_num;

	return 0;

}



static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)

static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, u8 len)

{

	u32 vals[4] = {};

	int i, ret;
@@ -124,8 +165,7 @@ static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) 
	if (len > 16)

		return -EIO;



	ret = regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,

			       vals, ARRAY_SIZE(vals));

	ret = regmap_bulk_read(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals));

	if (ret)

		return ret;
@@ -137,7 +177,7 @@ static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) 
	return 0;

}



static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)

static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, u8 len)

{

	u32 vals[4] = {};

	int i;
@@ -152,56 +192,94 @@ static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len) 
		vals[reg] |= buf[i] << shift;

	}



	return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,

				vals, ARRAY_SIZE(vals));

	return regmap_bulk_write(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals));

}



static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data)

{

	return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, data);

	return regmap_write(i2c->regmap, i2c->data_reg, data);

}



static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write,

				    int size, union i2c_smbus_data *data, int len)

static int rtl9300_i2c_prepare_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer)

{

	u32 val, mask;

	int ret;



	val = read_write == I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : 0;

	mask = RTL9300_I2C_MST_CTRL1_RWOP;

	if (xfer->data_len < 1 || xfer->data_len > 16)

		return -EINVAL;



	ret = regmap_field_write(i2c->fields[F_DEV_ADDR], xfer->dev_addr);

	if (ret)

		return ret;



	ret = rtl9300_i2c_reg_addr_set(i2c, xfer->reg_addr, xfer->reg_addr_len);

	if (ret)

		return ret;



	ret = regmap_field_write(i2c->fields[F_RWOP], xfer->write);

	if (ret)

		return ret;



	ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (xfer->data_len - 1) & 0xf);

	if (ret)

		return ret;



	val |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;

	mask |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;

	if (xfer->write) {

		switch (xfer->type) {

		case RTL9300_I2C_XFER_BYTE:

			ret = rtl9300_i2c_writel(i2c, *xfer->data);

			break;

		case RTL9300_I2C_XFER_WORD:

			ret = rtl9300_i2c_writel(i2c, get_unaligned((const u16 *)xfer->data));

			break;

		default:

			ret = rtl9300_i2c_write(i2c, xfer->data, xfer->data_len);

			break;

		}

	}



	return ret;

}



static int rtl9300_i2c_do_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer)

{

	u32 val;

	int ret;



	ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);

	ret = regmap_field_write(i2c->fields[F_I2C_TRIG], 1);

	if (ret)

		return ret;



	ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1,

				       val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 100000);

	ret = regmap_field_read_poll_timeout(i2c->fields[F_I2C_TRIG], val, !val, 100, 100000);

	if (ret)

		return ret;



	if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL)

	ret = regmap_field_read(i2c->fields[F_I2C_FAIL], &val);

	if (ret)

		return ret;

	if (val)

		return -EIO;



	if (read_write == I2C_SMBUS_READ) {

		if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA) {

			ret = regmap_read(i2c->regmap,

					  i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);

	if (!xfer->write) {

		switch (xfer->type) {

		case RTL9300_I2C_XFER_BYTE:

			ret = regmap_read(i2c->regmap, i2c->data_reg, &val);

			if (ret)

				return ret;

			data->byte = val & 0xff;

		} else if (size == I2C_SMBUS_WORD_DATA) {

			ret = regmap_read(i2c->regmap,

					  i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);



			*xfer->data = val & 0xff;

			break;

		case RTL9300_I2C_XFER_WORD:

			ret = regmap_read(i2c->regmap, i2c->data_reg, &val);

			if (ret)

				return ret;

			data->word = val & 0xffff;

		} else {

			ret = rtl9300_i2c_read(i2c, &data->block[0], len);



			put_unaligned(val & 0xffff, (u16*)xfer->data);

			break;

		default:

			ret = rtl9300_i2c_read(i2c, xfer->data, xfer->data_len);

			if (ret)

				return ret;

			break;

		}

	}
@@ -214,100 +292,68 @@ static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned s 
{

	struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap);

	struct rtl9300_i2c *i2c = chan->i2c;

	int len = 0, ret;

	struct rtl9300_i2c_xfer xfer = {0};

	int ret;



	if (addr > 0x7f)

		return -EINVAL;



	mutex_lock(&i2c->lock);

	if (chan->sda_pin != i2c->sda_pin) {

		ret = rtl9300_i2c_config_io(i2c, chan->sda_pin);

	guard(rtl9300_i2c)(i2c);



	ret = rtl9300_i2c_config_chan(i2c, chan);

	if (ret)

			goto out_unlock;

		i2c->sda_pin = chan->sda_pin;

	}

		return ret;



	xfer.dev_addr = addr & 0x7f;

	xfer.write = (read_write == I2C_SMBUS_WRITE);

	xfer.reg_addr = command;

	xfer.reg_addr_len = 1;



	switch (size) {

	case I2C_SMBUS_BYTE:

		if (read_write == I2C_SMBUS_WRITE) {

			ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0);

			if (ret)

				goto out_unlock;

			ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);

			if (ret)

				goto out_unlock;

		} else {

			ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1);

			if (ret)

				goto out_unlock;

			ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0);

			if (ret)

				goto out_unlock;

		}

		xfer.data = (read_write == I2C_SMBUS_READ) ? &data->byte : &command;

		xfer.data_len = 1;

		xfer.reg_addr = 0;

		xfer.reg_addr_len = 0;

		xfer.type = RTL9300_I2C_XFER_BYTE;

		break;



	case I2C_SMBUS_BYTE_DATA:

		ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);

		if (ret)

			goto out_unlock;

		ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1);

		if (ret)

			goto out_unlock;

		if (read_write == I2C_SMBUS_WRITE) {

			ret = rtl9300_i2c_writel(i2c, data->byte);

			if (ret)

				goto out_unlock;

		}

		xfer.data = &data->byte;

		xfer.data_len = 1;

		xfer.type = RTL9300_I2C_XFER_BYTE;

		break;



	case I2C_SMBUS_WORD_DATA:

		ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);

		if (ret)

			goto out_unlock;

		ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 2);

		if (ret)

			goto out_unlock;

		if (read_write == I2C_SMBUS_WRITE) {

			ret = rtl9300_i2c_writel(i2c, data->word);

			if (ret)

				goto out_unlock;

		}

		xfer.data = (u8 *)&data->word;

		xfer.data_len = 2;

		xfer.type = RTL9300_I2C_XFER_WORD;

		break;



	case I2C_SMBUS_BLOCK_DATA:

		ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);

		if (ret)

			goto out_unlock;

		if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) {

			ret = -EINVAL;

			goto out_unlock;

		}

		ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0] + 1);

		if (ret)

			goto out_unlock;

		if (read_write == I2C_SMBUS_WRITE) {

			ret = rtl9300_i2c_write(i2c, &data->block[0], data->block[0] + 1);

			if (ret)

				goto out_unlock;

		}

		len = data->block[0] + 1;

		xfer.data = &data->block[0];

		xfer.data_len = data->block[0] + 1;

		xfer.type = RTL9300_I2C_XFER_BLOCK;

		break;

	case I2C_SMBUS_I2C_BLOCK_DATA:

		xfer.data = &data->block[1];

		xfer.data_len = data->block[0];

		xfer.type = RTL9300_I2C_XFER_BLOCK;

		break;



	default:

		dev_err(&adap->dev, "Unsupported transaction %d\n", size);

		ret = -EOPNOTSUPP;

		goto out_unlock;

		return -EOPNOTSUPP;

	}



	ret = rtl9300_i2c_execute_xfer(i2c, read_write, size, data, len);



out_unlock:

	mutex_unlock(&i2c->lock);



	ret = rtl9300_i2c_prepare_xfer(i2c, &xfer);

	if (ret)

		return ret;



	return rtl9300_i2c_do_xfer(i2c, &xfer);

}



static u32 rtl9300_i2c_func(struct i2c_adapter *a)

{

	return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |

	       I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA;

	       I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |

	       I2C_FUNC_SMBUS_I2C_BLOCK;

}



static const struct i2c_algorithm rtl9300_i2c_algo = {
@@ -325,9 +371,11 @@ static int rtl9300_i2c_probe(struct platform_device *pdev) 
{

	struct device *dev = &pdev->dev;

	struct rtl9300_i2c *i2c;

	u32 clock_freq, sda_pin;

	int ret, i = 0;

	struct fwnode_handle *child;

	struct rtl9300_i2c_drv_data *drv_data;

	struct reg_field fields[F_NUM_FIELDS];

	u32 clock_freq, scl_num, sda_num;

	int ret, i = 0;



	i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);

	if (!i2c)
@@ -344,16 +392,34 @@ static int rtl9300_i2c_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = device_property_read_u32(dev, "realtek,scl", &scl_num);

	if (ret || scl_num != 1)

		scl_num = 0;

	i2c->scl_num = (u8)scl_num;



	platform_set_drvdata(pdev, i2c);



	if (device_get_child_node_count(dev) > RTL9300_I2C_MUX_NCHAN)

	drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);

	if (device_get_child_node_count(dev) > drv_data->max_nchan)

		return dev_err_probe(dev, -EINVAL, "Too many channels\n");



	i2c->data_reg = i2c->reg_base + drv_data->data_reg;

	for (i = 0; i < F_NUM_FIELDS; i++) {

		fields[i] = drv_data->field_desc[i].field;

		if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER)

			fields[i].reg += i2c->reg_base;

	}

	ret = devm_regmap_field_bulk_alloc(dev, i2c->regmap, i2c->fields,

					   fields, F_NUM_FIELDS);

	if (ret)

		return ret;



	i = 0;

	device_for_each_child_node(dev, child) {

		struct rtl9300_i2c_chan *chan = &i2c->chans[i];

		struct i2c_adapter *adap = &chan->adap;



		ret = fwnode_property_read_u32(child, "reg", &sda_pin);

		ret = fwnode_property_read_u32(child, "reg", &sda_num);

		if (ret)

			return ret;
@@ -365,17 +431,16 @@ static int rtl9300_i2c_probe(struct platform_device *pdev) 
		case I2C_MAX_STANDARD_MODE_FREQ:

			chan->bus_freq = RTL9300_I2C_STD_FREQ;

			break;



		case I2C_MAX_FAST_MODE_FREQ:

			chan->bus_freq = RTL9300_I2C_FAST_FREQ;

			break;

		default:

			dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n",

				 sda_pin, clock_freq);

				 sda_num, clock_freq);

			break;

		}



		chan->sda_pin = sda_pin;

		chan->sda_num = sda_num;

		chan->i2c = i2c;

		adap = &i2c->chans[i].adap;

		adap->owner = THIS_MODULE;
@@ -385,23 +450,77 @@ static int rtl9300_i2c_probe(struct platform_device *pdev) 
		adap->dev.parent = dev;

		i2c_set_adapdata(adap, chan);

		adap->dev.of_node = to_of_node(child);

		snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_pin);

		snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_num);

		i++;



		ret = devm_i2c_add_adapter(dev, adap);

		if (ret)

			return ret;

	}

	i2c->sda_pin = 0xff;

	i2c->sda_num = 0xff;



	/* only use standard read format */

	ret = regmap_field_write(i2c->fields[F_RD_MODE], 0);

	if (ret)

		return ret;



	return 0;

}



#define GLB_REG_FIELD(reg, msb, lsb)    \

	{ .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_GLOBAL }

#define MST_REG_FIELD(reg, msb, lsb)    \

	{ .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_MASTER }



static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = {

	.field_desc = {

		[F_MEM_ADDR]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31),

		[F_SDA_OUT_SEL]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6),

		[F_SCL_SEL]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3),

		[F_RWOP]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2),

		[F_I2C_FAIL]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1),

		[F_I2C_TRIG]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0),

		[F_RD_MODE]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15),

		[F_DEV_ADDR]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14),

		[F_DATA_WIDTH]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7),

		[F_MEM_ADDR_WIDTH]	= MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3),

		[F_SCL_FREQ]		= MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1),

		[F_SDA_SEL]		= GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7),

	},

	.select_scl = rtl9300_i2c_select_scl,

	.data_reg = RTL9300_I2C_MST_DATA_WORD0,

	.max_nchan = RTL9300_I2C_MUX_NCHAN,

};



static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data = {

	.field_desc = {

		[F_SCL_SEL]		= GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13),

		[F_SDA_SEL]		= GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11),

		[F_SCL_FREQ]		= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31),

		[F_DEV_ADDR]		= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17),

		[F_SDA_OUT_SEL]		= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21),

		[F_MEM_ADDR_WIDTH]	= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10),

		[F_DATA_WIDTH]		= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8),

		[F_RD_MODE]		= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4),

		[F_RWOP]		= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2),

		[F_I2C_FAIL]		= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1),

		[F_I2C_TRIG]		= MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0),

		[F_MEM_ADDR]		= MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23),

	},

	.select_scl = rtl9310_i2c_select_scl,

	.data_reg = RTL9310_I2C_MST_DATA_CTRL,

	.max_nchan = RTL9310_I2C_MUX_NCHAN,

};



static const struct of_device_id i2c_rtl9300_dt_ids[] = {

	{ .compatible = "realtek,rtl9301-i2c" },

	{ .compatible = "realtek,rtl9302b-i2c" },

	{ .compatible = "realtek,rtl9302c-i2c" },

	{ .compatible = "realtek,rtl9303-i2c" },

	{ .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data },

	{ .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data },

	{ .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data },

	{ .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data },

	{ .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data },

	{ .compatible = "realtek,rtl9311-i2c", .data = (void *) &rtl9310_i2c_drv_data },

	{ .compatible = "realtek,rtl9312-i2c", .data = (void *) &rtl9310_i2c_drv_data },

	{ .compatible = "realtek,rtl9313-i2c", .data = (void *) &rtl9310_i2c_drv_data },

	{}

};

MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);