Commit 192c344e authored Mar 26, 2021 by Geert Uytterhoeven

clk: renesas: rcar-gen3: Update Z clock rate formula in comments

The fixed divider in the calculation of the Z and Z2 clock rates was
generalized from a hardcoded value of two to a parameterized value, but
the comments were not updated accordingly.

Fixes: 20cc05ba ("clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-2-geert+renesas@glider.be

parent 6efb943b

drivers/clk/renesas/rcar-gen3-cpg.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -38,7 +38,8 @@
		* Traits of this clock:
		* prepare - clk_prepare only ensures that parents are prepared
		* enable - clk_enable only ensures that parents are enabled
		* rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
		* rate - rate is adjustable.
		* clk->rate = (parent->rate * mult / 32 ) / fixed_div
		* parent - fixed parent. No clk_set_parent support
		*/
		#define CPG_FRQCRB 0x00000004