Commit 1a391931 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-urgent-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq fixes from Thomas Gleixner:
 "A series of fixes for the Renesas RZG21 interrupt chip driver to
  prevent spurious and misrouted interrupts.

   - Ensure that posted writes are flushed in the eoi() callback

   - Ensure that interrupts are masked at the chip level when the
     trigger type is changed

   - Clear the interrupt status register when setting up edge type
     trigger modes

   - Ensure that the trigger type and routing information is set before
     the interrupt is enabled"

* tag 'irq-urgent-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same time
  irqchip/renesas-rzg2l: Prevent spurious interrupts when setting trigger type
  irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi()
  irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi()
  irqchip/renesas-rzg2l: Flush posted write in irq_eoi()
parents 976b029d dce0919c

drivers/irqchip/irq-renesas-rzg2l.c

+54 −18
Original line number Diff line number Diff line
@@ -85,10 +85,9 @@ static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) 
	return data->domain->host_data;

}



static void rzg2l_irq_eoi(struct irq_data *d)

static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)

{

	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;

	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);

	unsigned int hw_irq = hwirq - IRQC_IRQ_START;

	u32 bit = BIT(hw_irq);

	u32 iitsr, iscr;
@@ -99,20 +98,30 @@ static void rzg2l_irq_eoi(struct irq_data *d) 
	 * ISCR can only be cleared if the type is falling-edge, rising-edge or

	 * falling/rising-edge.

	 */

	if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq)))

	if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) {

		writel_relaxed(iscr & ~bit, priv->base + ISCR);

		/*

		 * Enforce that the posted write is flushed to prevent that the

		 * just handled interrupt is raised again.

		 */

		readl_relaxed(priv->base + ISCR);

	}

}



static void rzg2l_tint_eoi(struct irq_data *d)

static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)

{

	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START;

	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);

	u32 bit = BIT(hw_irq);

	u32 bit = BIT(hwirq - IRQC_TINT_START);

	u32 reg;



	reg = readl_relaxed(priv->base + TSCR);

	if (reg & bit)

	if (reg & bit) {

		writel_relaxed(reg & ~bit, priv->base + TSCR);

		/*

		 * Enforce that the posted write is flushed to prevent that the

		 * just handled interrupt is raised again.

		 */

		readl_relaxed(priv->base + TSCR);

	}

}



static void rzg2l_irqc_eoi(struct irq_data *d)
@@ -122,9 +131,9 @@ static void rzg2l_irqc_eoi(struct irq_data *d) 


	raw_spin_lock(&priv->lock);

	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)

		rzg2l_irq_eoi(d);

		rzg2l_clear_irq_int(priv, hw_irq);

	else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)

		rzg2l_tint_eoi(d);

		rzg2l_clear_tint_int(priv, hw_irq);

	raw_spin_unlock(&priv->lock);

	irq_chip_eoi_parent(d);

}
@@ -142,7 +151,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) 


		raw_spin_lock(&priv->lock);

		reg = readl_relaxed(priv->base + TSSR(tssr_index));

		reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));

		reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));

		writel_relaxed(reg, priv->base + TSSR(tssr_index));

		raw_spin_unlock(&priv->lock);

	}
@@ -154,7 +163,6 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) 
	unsigned int hw_irq = irqd_to_hwirq(d);



	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {

		unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d);

		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);

		u32 offset = hw_irq - IRQC_TINT_START;

		u32 tssr_offset = TSSR_OFFSET(offset);
@@ -163,7 +171,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) 


		raw_spin_lock(&priv->lock);

		reg = readl_relaxed(priv->base + TSSR(tssr_index));

		reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset);

		reg |= TIEN << TSSEL_SHIFT(tssr_offset);

		writel_relaxed(reg, priv->base + TSSR(tssr_index));

		raw_spin_unlock(&priv->lock);

	}
@@ -172,8 +180,10 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) 


static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)

{

	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;

	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);

	unsigned int hwirq = irqd_to_hwirq(d);

	u32 iitseln = hwirq - IRQC_IRQ_START;

	bool clear_irq_int = false;

	u16 sense, tmp;



	switch (type & IRQ_TYPE_SENSE_MASK) {
@@ -183,14 +193,17 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) 


	case IRQ_TYPE_EDGE_FALLING:

		sense = IITSR_IITSEL_EDGE_FALLING;

		clear_irq_int = true;

		break;



	case IRQ_TYPE_EDGE_RISING:

		sense = IITSR_IITSEL_EDGE_RISING;

		clear_irq_int = true;

		break;



	case IRQ_TYPE_EDGE_BOTH:

		sense = IITSR_IITSEL_EDGE_BOTH;

		clear_irq_int = true;

		break;



	default:
@@ -199,21 +212,40 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) 


	raw_spin_lock(&priv->lock);

	tmp = readl_relaxed(priv->base + IITSR);

	tmp &= ~IITSR_IITSEL_MASK(hw_irq);

	tmp |= IITSR_IITSEL(hw_irq, sense);

	tmp &= ~IITSR_IITSEL_MASK(iitseln);

	tmp |= IITSR_IITSEL(iitseln, sense);

	if (clear_irq_int)

		rzg2l_clear_irq_int(priv, hwirq);

	writel_relaxed(tmp, priv->base + IITSR);

	raw_spin_unlock(&priv->lock);



	return 0;

}



static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv,

						  u32 reg, u32 tssr_offset, u8 tssr_index)

{

	u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);

	u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset));



	/* Clear the relevant byte in reg */

	reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));

	/* Set TINT and leave TIEN clear */

	reg |= tint << TSSEL_SHIFT(tssr_offset);

	writel_relaxed(reg, priv->base + TSSR(tssr_index));



	return reg | tien;

}



static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)

{

	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);

	unsigned int hwirq = irqd_to_hwirq(d);

	u32 titseln = hwirq - IRQC_TINT_START;

	u32 tssr_offset = TSSR_OFFSET(titseln);

	u8 tssr_index = TSSR_INDEX(titseln);

	u8 index, sense;

	u32 reg;

	u32 reg, tssr;



	switch (type & IRQ_TYPE_SENSE_MASK) {

	case IRQ_TYPE_EDGE_RISING:
@@ -235,10 +267,14 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) 
	}



	raw_spin_lock(&priv->lock);

	tssr = readl_relaxed(priv->base + TSSR(tssr_index));

	tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index);

	reg = readl_relaxed(priv->base + TITSR(index));

	reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));

	reg |= sense << (titseln * TITSEL_WIDTH);

	writel_relaxed(reg, priv->base + TITSR(index));

	rzg2l_clear_tint_int(priv, hwirq);

	writel_relaxed(tssr, priv->base + TSSR(tssr_index));

	raw_spin_unlock(&priv->lock);



	return 0;