Unverified Commit 1a3f6980 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "riscv: Add vendor extensions support for SiFive" 



Cyan Yang <cyan.yang@sifive.com> says:

This patch set adds four vendor-specific ISA extensions from SiFive:
"xsfvqmaccdod", "xsfvqmaccqoq", "xsfvfnrclipxfqf", and "xsfvfwmaccqqq".

Additionally, a new hwprobe key, RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0,
has been added to query which SiFive vendor extensions are supported on
the current platform.

Signed-off-by: default avatarCyan Yang <cyan.yang@sifive.com>
Link: https://lore.kernel.org/r/20250418053239.4351-1-cyan.yang@sifive.com



* b4-shazam-merge:
  riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension
  riscv: hwprobe: Document SiFive xsfvfwmaccqqq vendor extension
  riscv: Add SiFive xsfvfwmaccqqq vendor extension
  dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description
  riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension
  riscv: hwprobe: Document SiFive xsfvfnrclipxfqf vendor extension
  riscv: Add SiFive xsfvfnrclipxfqf vendor extension
  dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description
  riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq
  riscv: hwprobe: Document SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions
  riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions
  dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description

Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 2940954c d9669e33

Documentation/arch/riscv/hwprobe.rst

+22 −0
Original line number Diff line number Diff line
@@ -335,3 +335,25 @@ The following keys are defined: 


* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicbom block in bytes.



* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the

  sifive vendor extensions that are compatible with the

  :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.



  * SIFIVE



    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor

        extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication

	Extensions Specification.



    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor

        extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication

	Instruction Extensions Specification.



    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf

        vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged

	Clip Instructions Extensions Specification.



    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq

        vendor extension is supported in version 1.0 of Matrix Multiply Accumulate

	Instruction Extensions Specification.
 
 No newline at end of file

Documentation/devicetree/bindings/riscv/extensions.yaml

+25 −0
Original line number Diff line number Diff line
@@ -662,6 +662,31 @@ properties: 
            Registers in the AX45MP datasheet.

            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf



        # SiFive

        - const: xsfvqmaccdod

          description:

            SiFive Int8 Matrix Multiplication Extensions Specification.

            See more details in

            https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification



        - const: xsfvqmaccqoq

          description:

            SiFive Int8 Matrix Multiplication Extensions Specification.

            See more details in

            https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification



        - const: xsfvfnrclipxfqf

          description:

            SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.

            See more details in

            https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions



        - const: xsfvfwmaccqqq

          description:

            SiFive Matrix Multiply Accumulate Instruction Extensions Specification.

            See more details in

            https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction



        # T-HEAD

        - const: xtheadvector

          description:

arch/riscv/Kconfig.vendor

+13 −0
Original line number Diff line number Diff line
@@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES 
	  If you don't know what to do here, say Y.

endmenu



menu "SiFive"

config RISCV_ISA_VENDOR_EXT_SIFIVE

	bool "SiFive vendor extension support"

	select RISCV_ISA_VENDOR_EXT

	default y

	help

	  Say N here if you want to disable all SiFive vendor extension

	  support. This will cause any SiFive vendor extensions that are

	  requested by hardware probing to be ignored.



	  If you don't know what to do here, say Y.

endmenu



menu "T-Head"

config RISCV_ISA_VENDOR_EXT_THEAD

	bool "T-Head vendor extension support"

arch/riscv/include/asm/hwprobe.h

+2 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


#include <uapi/asm/hwprobe.h>



#define RISCV_HWPROBE_MAX_KEY 12

#define RISCV_HWPROBE_MAX_KEY 13



static inline bool riscv_hwprobe_key_is_valid(__s64 key)

{
@@ -22,6 +22,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) 
	case RISCV_HWPROBE_KEY_IMA_EXT_0:

	case RISCV_HWPROBE_KEY_CPUPERF_0:

	case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:

	case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:

		return true;

	}

arch/riscv/include/asm/vendor_extensions/sifive.h

0 → 100644
+16 −0
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/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H

#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H



#include <asm/vendor_extensions.h>



#include <linux/types.h>



#define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD		0

#define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ		1

#define RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF		2

#define RISCV_ISA_VENDOR_EXT_XSFVFWMACCQQQ		3



extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive;



#endif