Commit 1a4edef8 authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-intel-fixes-2023-04-05' of... 

Merge tag 'drm-intel-fixes-2023-04-05' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v6.3-rc6:
- Fix DP MST DSC M/N calculation to use compressed bpp
- Fix racy use-after-free in perf ioctl
- Fix context runtime accounting
- Fix handling of GT reset during HuC loading
- Fix use of unsigned vm_fault_t for error values

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87zg7mzomz.fsf@intel.com
parents 7e364e56 dc342156

drivers/gpu/drm/i915/display/intel_dp_mst.c

+1 −1
Original line number Diff line number Diff line
@@ -232,7 +232,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, 
			return slots;

	}



	intel_link_compute_m_n(crtc_state->pipe_bpp,

	intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,

			       crtc_state->lane_count,

			       adjusted_mode->crtc_clock,

			       crtc_state->port_clock,

drivers/gpu/drm/i915/gem/i915_gem_ttm.c

+3 −2
Original line number Diff line number Diff line
@@ -1067,11 +1067,12 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf) 
			.interruptible = true,

			.no_wait_gpu = true, /* should be idle already */

		};

		int err;



		GEM_BUG_ON(!bo->ttm || !(bo->ttm->page_flags & TTM_TT_FLAG_SWAPPED));



		ret = ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);

		if (ret) {

		err = ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);

		if (err) {

			dma_resv_unlock(bo->base.resv);

			return VM_FAULT_SIGBUS;

		}

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

+10 −2
Original line number Diff line number Diff line
@@ -2018,6 +2018,8 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) 
	 * inspecting the queue to see if we need to resumbit.

	 */

	if (*prev != *execlists->active) { /* elide lite-restores */

		struct intel_context *prev_ce = NULL, *active_ce = NULL;



		/*

		 * Note the inherent discrepancy between the HW runtime,

		 * recorded as part of the context switch, and the CPU
@@ -2029,9 +2031,15 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) 
		 * and correct overselves later when updating from HW.

		 */

		if (*prev)

			lrc_runtime_stop((*prev)->context);

			prev_ce = (*prev)->context;

		if (*execlists->active)

			lrc_runtime_start((*execlists->active)->context);

			active_ce = (*execlists->active)->context;

		if (prev_ce != active_ce) {

			if (prev_ce)

				lrc_runtime_stop(prev_ce);

			if (active_ce)

				lrc_runtime_start(active_ce);

		}

		new_timeslice(execlists);

	}

drivers/gpu/drm/i915/gt/uc/intel_huc.c

+7 −0
Original line number Diff line number Diff line
@@ -235,6 +235,13 @@ static void delayed_huc_load_fini(struct intel_huc *huc) 
	i915_sw_fence_fini(&huc->delayed_load.fence);

}



int intel_huc_sanitize(struct intel_huc *huc)

{

	delayed_huc_load_complete(huc);

	intel_uc_fw_sanitize(&huc->fw);

	return 0;

}



static bool vcs_supported(struct intel_gt *gt)

{

	intel_engine_mask_t mask = gt->info.engine_mask;

drivers/gpu/drm/i915/gt/uc/intel_huc.h

+1 −6
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ struct intel_huc { 
	} delayed_load;

};



int intel_huc_sanitize(struct intel_huc *huc);

void intel_huc_init_early(struct intel_huc *huc);

int intel_huc_init(struct intel_huc *huc);

void intel_huc_fini(struct intel_huc *huc);
@@ -54,12 +55,6 @@ bool intel_huc_is_authenticated(struct intel_huc *huc); 
void intel_huc_register_gsc_notifier(struct intel_huc *huc, struct bus_type *bus);

void intel_huc_unregister_gsc_notifier(struct intel_huc *huc, struct bus_type *bus);



static inline int intel_huc_sanitize(struct intel_huc *huc)

{

	intel_uc_fw_sanitize(&huc->fw);

	return 0;

}



static inline bool intel_huc_is_supported(struct intel_huc *huc)

{

	return intel_uc_fw_is_supported(&huc->fw);